Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX Devicesfunctionality while the system is in operation by reconfiguring the device.You can also perform in-field upgrades by distributing a newprogramming file to system users.The following sections describe the MSEL[2..0], VCCSEL, PORSEL, andnIO_PULLUP pins used in Stratix and Stratix GX device configuration.MSEL[2..0] PinsYou can select a Stratix or Stratix GX device configuration scheme bydriving its MSEL2, MSEL1, and MSEL0 pins either high or low, as shownin Table 11–2.Table 11–2. Stratix & Stratix GX Device Configuration SchemesDescription MSEL2 MSEL1 MSEL0FPP configuration 0 0 0PPA configuration 0 0 1PS configuration 0 1 0Remote/local update FPP (1) 1 0 0Remote/local update PPA (1) 1 0 1Remote/local update PS (1) 1 1 0JTAG-based configuration (3) (2) (2) (2)Notes to Table 11–2:(1) These schemes require that you drive a secondary pin RUnLU to specify whetherto perform a remote update or local update.(2) Do not leave MSEL pins floating. Connect them to V CCIO or GND. These pinssupport the non-JTAG configuration scheme used in production. If only JTAGconfiguration is used you should connect the MSEL pins to ground.(3) JTAG-based configuration takes precedence over other configuration schemes,which means the MSEL pins are ignored.The MSEL[] pins can be tied to V CCIO of the I/O bank they reside in orground.V CCSEL PinsYou can configure Stratix and Stratix GX devices using the 3.3-, 2.5-, 1.8-,or 1.5-V LVTTL I/O standard on configuration and JTAG input pins.VCCSEL is a dedicated input on Stratix and Stratix GX devices that selectsbetween 3.3-V/2.5-V input buffers and 1.8-V/1.5-V input buffers fordedicated configuration input pins. A logic low supports 3.3-V/2.5-Vsignaling, and a logic high supports 1.8-V/1.5-V signaling. A logic highcan also support 3.3-V/2.5-V signaling. VCCSEL affects the configurationAltera Corporation 11–3July 2005 Stratix Device Handbook, Volume 2