Configuration Handbook - Kamami.pl

Device Configuration PinsTable 11–15. Dedicated Configuration Pins on the Stratix III Device (Part 2 of 7)Pin Name User Mode ConfigurationSchemePin TypeDescriptionnIO_PULLUP N/A All Input Dedicated input that chooses whether theinternal pull-up resistors on the user I/O pinsand dual-purpose I/O pins (nCSO, nASDO,DATA[7..0], nWS, nRS, RDYnBSY, nCS,CLKUSR, INIT_DONE) are on or off beforeand during configuration. A logic high (1.8 V,2.5 V, 3.0 V) turns off the weak internal pull-upresistors, while a logic low turns them on.The nIO-PULLUP input buffer is powered byV CC and has an internal 5-kΩ pull-downresistor that is always active. You can tie thenIO-PULLUP directly to V CCPGM or use a 1-kΩpull-up resistor or tie it directly to GND.MSEL[2..0] N/A All Input 3-bit configuration input that sets the Stratix IIIdevice configuration scheme. Refer toTable 11–1 for the appropriate connections.You must hard-wire these pins to V CCPGM orGND.The MSEL[2..0] pins have internal 5-kΩpull-down resistors that are always active.nCONFIG N/A All Input Configuration control input. Pulling this pin lowduring user-mode will cause the device to loseits configuration data, enter a reset state, andtri-state all I/O pins. Returning this pin to alogic high level will initiate a reconfiguration.Configuration is possible only if this pin is high,except in JTAG programming mode whennCONFIG is ignored.If your configuration scheme uses anenhanced configuration device, you can tienCONFIG to V CCPGM through a 10-kΩ resistorto the configuration device's nINIT_CONFpin.11–76 Altera CorporationStratix III Device Handbook, Volume 1 May 2007