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Configuration Handbook - Kamami.pl

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Functional DescriptionTable 2–3 summarizes the concurrent PS configuration modes supportedin the enhanced configuration device.Table 2–3. Enhanced <strong>Configuration</strong> Devices in PS ModeMode Name Mode (n =) (1) Used Outputs Unused OutputsPassive serial mode 1 DATA0 DATA[7..1] drive lowMulti-device passive 2 DATA[1..0] DATA[7..2] drive lowserial modeMulti-device passiveserial modeMulti-device passiveserial mode4 DATA[3..0] DATA[7..4] drive low8 DATA[7..0] -Note to Table 2–3:(1) This is the number of valid DATA outputs for each configuration mode.fFor configuration schematics and more information on concurrentconfigurations, refer to the Using Altera Enhanced <strong>Configuration</strong> Deviceschapter in the <strong>Configuration</strong> <strong>Handbook</strong>, Volume 2, or refer to theappropriate FPGA family chapter in the <strong>Configuration</strong> <strong>Handbook</strong>.External Flash InterfaceThe enhanced configuration devices support external FPGA or processoraccess to its flash memory. The unused portions of the flash memory canbe used by the external device to store code or data. This interface can alsobe used in systems that im<strong>pl</strong>ement remote configuration capabilities.<strong>Configuration</strong> data within a particular configuration page can beupdated via the external flash interface and the system could bereconfigured with the new FPGA image. This interface is also useful tostore Nios boot code and/or ap<strong>pl</strong>ication code.fFor more information on the Stratix remote configuration feature, referto the Using Remote System <strong>Configuration</strong> with Stratix & Stratix GX Deviceschapter in the Stratix Device <strong>Handbook</strong>.The address, data, and control ports of the flash memory are internallyconnected to the enhanced configuration device controller and to externaldevice pins. An external source can drive these external device pins toaccess the flash memory when the flash interface is available.This external flash interface is a shared bus interface with theconfiguration controller chip. The configuration controller is the primarybus master. Since there is no bus arbitration support, the external devicecan only access the flash interface when the controller has tri-stated its2–12 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 2 May 2007

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