Configuration Handbook - Kamami.pl

Functional DescriptionFast Passive Parallel ConfigurationStratix series and APEX II devices can be configured using the enhancedconfiguration device in FPP mode. In this mode, the enhancedconfiguration device sends a byte of data on the DATA[7..0] pins,which connect to the DATA[7..0] input pins of the FPGA, per DCLKcycle. Stratix series and APEX II FPGAs receive byte-wide configurationdata per DCLK cycle. Figure 2–2 shows the enhanced configuration devicein FPP configuration mode. In this figure, the external flash interface isnot used and hence most flash pins are left unconnected (with the fewnoted exceptions). For specific details on configuration interfaceconnections including pull-up resistor values, supply voltages, and MSELpin settings, refer to the appropriate FPGA family chapter in theConfiguration Handbook.Figure 2–2. FPP Configuration(1) (1)Enhanced ConfigurationDevice(6)nN.C.MSELnCEOStratix SeriesorAPEX II DeviceDCLKDATA[7..0]nSTATUSCONF_DONEnCONFIGnCEV CC V CCGND(3) (3)GNDWE#CWE#FRP#CRP#FDCLKDATA[7..0] A[20..0]OE (3) RY/BY#nCS(3)CE#nINIT_CONF (2)OE#(1) V CCDQ[15..0]WP#BYTE# (5)TM1VCCWPORSELPGM[2..0]V CC (1)(4)(4)N.C.N.C.N.C.N.C.N.C.TMOEXCLK(4)C-A0 (5)C-A1 (5)C-A15 (5)C-A16 (5)A0-FA1-FA15-FA16-F2–8 Altera CorporationConfiguration Handbook, Volume 2 May 2007