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Configuration Handbook - Kamami.pl

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Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K DevicesTable 8–11. PPS Timing Parameters for Mercury Devices (Part 2 of 2)Symbol Parameter Min Max Unitst CH DCLK high time 10 nst CL DCLK low time 10 nst CLK DCLK period 20 nsf MAX DCLK frequency 50 MHzt CD2UM CONF_DONE high to user mode (4) 6 28 µsNotes to Table 8–11:(1) This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulsewidth.(2) The RDYnBSY pin is not required in the PPS mode. <strong>Configuration</strong> data can be sent every 8 DCLK cycles withoutmonitoring this status pin.(3) This parameter depends on the DCLK frequency. The RDYnBSY signal goes high 7.5 clock cycles after the risingedge of DCLK. This value was calculated with a DCLK frequency of 10 MHz.(4) The minimum and maximum numbers ap<strong>pl</strong>y only if the internal oscillator is chosen as the clock source for startingup the device. If the clock source is CLKUSR, multi<strong>pl</strong>y the clock period by 136 to obtain this value.Table 8–12. PPS Timing Parameters for APEX 20K Devices (Part 1 of 2)Symbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 200 nst CF2ST0 nCONFIG low to nSTATUS low 200 nst CFG nCONFIG low pulse width 8 µst STATUS nSTATUS low pulse width 10 40 (1) µst CF2ST1 nCONFIG high to nSTATUS high 1 (1) µst CF2CK nCONFIG high to first rising edge on DCLK 40 µst ST2CK nSTATUS high to first rising edge on DCLK 1 µst DSU Data setup time before rising edge on DCLK 10 nst DH Data hold time after rising edge on DCLK 0 nst CH2B First rising DCLK to first rising RDYnBSY (2) 0.75 (3) µst CH DCLK high time 15 nst CL DCLK low time 15 nst CLK DCLK period 30 nsf MAX DCLK frequency 33.3 MHzAltera Corporation 8–43August 2005 <strong>Configuration</strong> <strong>Handbook</strong>, Volume 1

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