Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesTable 7–5. Pins Affected by the Voltage Level at VCCSELPin VCCSEL = LOW (connected to GND) VCCSEL = HIGH (connected to V CCPD )nSTATUS (when used as aninput)nCONFIGCONF_DONE (when used as aninput)DATA[7..0]nCEDCLK (when used as an input)CSnWSnRSnCSCLKUSRDEV_OEDEV_CLRnRUnLUPLL_ENA3.3/2.5-V input buffer is selected.Input buffer is powered by V CCPD .1.8/1.5-V input buffer is selected.Input buffer is powered by V CCIO ofthe I/O bank. These input buffers are3.3 V tolerant.VCCSEL is sampled during power-up. Therefore, the VCCSEL settingcannot change on the fly or during a reconfiguration. The VCCSEL inputbuffer is powered by V CCINT and has an internal 5-kΩ pull-down resistorthat is always active.1 VCCSEL must be hardwired to V CCPD or GND.A logic high selects the 1.8-V/1.5-V input buffer, and a logic low selectsthe 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with thelogic levels driven out of the configuration device or MAX II device or amicroprocessor with flash memory.VCCSEL also sets the POR trip point for I/O bank 3 to ensure that this I/Obank has powered up to the appropriate voltage levels beforeconfiguration begins. For passive serial (PS) mode (MSEL[3..0] = 0010)and for Fast passive parallel (FPP) mode (MSEL[3..0] = 0000) the PORcircuitry selects the trip point associated with 1.5-V/1.8-V signaling. Forall other configuration modes defined by MSEL[3..0] settings (otherAltera Corporation 7–11May 2007 Stratix II Device Handbook, Volume 2