Configuration Handbook - Kamami.pl

Passive Parallel Asynchronous ConfigurationFigure 8–20 shows the configuration interface connections between theFPGA and a microprocessor for single device PPA configuration. Themicroprocessor or an optional address decoder can control the device’schip select pins, nCS and CS. The address decoder allows themicroprocessor to select the Mercury, APEX 20K (2.5 V), ACEX 1K, orFLEX 10K device by accessing a particular address, which simplifies theconfiguration process. The nCS and CS pins must be held active duringconfiguration and initialization.Figure 8–20. Single Device PPA Configuration Using a Microprocessor Note (1)Address DecoderADDRV CC(2)MemoryADDR DATA[7..0]Microprocessor1 kΩV CCGND(2)1 kΩMercury, APEX 20K (2.5-V),ACEX 1K or FLEX 10K Device VCCnCS (1)CS (1)CONF_DONEnSTATUSnCEDATA[7..0]nWSnRSnCONFIGRDYnBSYMSEL1MSEL0nCEODCLKN.C.V CC(2)1 kΩNotes to Figure 8–20:(1) If not used, the CS pin can be connected to V CC directly. If not used, the nCS pin can be connected to GND directly.(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.During PPA configuration, it is only required to use either the nCS or CSpin. Therefore, if only one chip-select input is used, the other must be tiedto the active state. For example, nCS can be tied to ground while CS istoggled to control configuration. The device’s nCS or CS pins can betoggled during PPA configuration if the design meets the specificationsset for t CSSU , t WSP , and t CSH listed in Tables 8–15 through 8–17.Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10Kdevice goes through a Power-On Reset (POR) for approximately 5 µs.During POR, the device resets and holds nSTATUS low, and tri-states alluser I/O pins. Once the FPGA successfully exits POR, all user I/O pins8–46 Altera CorporationConfiguration Handbook, Volume 1 August 2005