Configuration Handbook - Kamami.pl

Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devicesare tri-stated. Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KEdevices have weak pull-up resistors on the user I/O pins which are onbefore and during configuration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the appropriate device family data sheet.The configuration cycle consists of 3 stages: reset, configuration, andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration, the microprocessor must generate a low-to-hightransition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configurationand JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 1-kΩpull-up resistor. Once nSTATUS is released the FPGA is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS ispulled high, the microprocessor should then assert the target device’snCS pin low and/or CS pin high. Next, the microprocessor places an 8-bitconfiguration word (one byte) on the target device’s DATA[7..0] pinsand pulses the nWS pin low.On the rising edge of nWS, the target device latches in a byte ofconfiguration data and drives its RDYnBSY signal low, which indicates itis processing the byte of configuration data. The microprocessor can thenperform other system functions while the Mercury, APEX 20K (2.5 V),ACEX 1K, or FLEX 10K device is processing the byte of configurationdata.During the time RDYnBSY is low, the Mercury, APEX 20K (2.5 V),ACEX 1K, or FLEX 10K device internally processes the configuration datausing its internal oscillator (typically 10 MHz). When the device is readyfor the next byte of configuration data, it will drive RDYnBSY high. If themicroprocessor senses a high signal when it polls RDYnBSY, themicroprocessor sends the next byte of configuration data to the FPGA.Alternatively, the nRS signal can be strobed low, causing the RDYnBSYsignal to appear on DATA7. Because RDYnBSY does not need to bemonitored, this pin doesn’t need to be connected to the microprocessor.Data should not be driven onto the data bus while nRS is low because itwill cause contention on the DATA7 pin. If the nRS pin is not used tomonitor configuration, it should be tied high.Altera Corporation 8–47August 2005 Configuration Handbook, Volume 1