Configuration Handbook - Kamami.pl

Functional DescriptionThe configuration schematic for PS configuration of a single FPGA orsingle serial chain is identical to the FPP schematic (with the exceptionthat only DATA[0] output from the enhanced configuration deviceconnects to the FPGA DATA0 input pin; remaining DATA[7..1] pins areleft floating).fFor configuration schematics and more information on multi-device PSconfiguration, refer to the appropriate FPGA family chapter in theConfiguration Handbook.Concurrent ConfigurationThe enhanced configuration device supports concurrent configuration ofmultiple FPGAs (or FPGA chains) in PS mode. Concurrent configurationis when the enhanced configuration device simultaneously outputs n bitsof configuration data on the DATA[n-1..0] pins (n = 1, 2, 4, or 8), andeach DATA[] line serially configures a different FPGA (chain). Thenumber of concurrent serial chains is user-defined via the Quartus IIsoftware and can be any number between 1 and 8. For example, threeconcurrent chains you can select the 4-bit PS mode, and connect the leastsignificant DATA bits to the FPGAs or FPGA chains. Leave the mostsignificant DATA bit (DATA[3]) unconnected. Similarly, for 5-, 6- or 7-bitconcurrent chains you can select the 8-bit PS mode.Figure 2–3 shows the schematic for configuring multiple FPGAsconcurrently in the PS mode using an enhanced configuration device.fFor specific details on configuration interface connections includingpull-up resistor values, supply voltages, and MSEL pin settings, refer tothe appropriate FPGA family chapter in the Configuration Handbook.2–10 Altera CorporationConfiguration Handbook, Volume 2 May 2007