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Configuration Handbook - Kamami.pl

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Configuring Cyclone FPGAsFigure 13–19. JTAG <strong>Configuration</strong> of Single Cyclone FPGAV CCGNDV CC10 kΩV CC10 kΩ10 kΩnCECyclone DeviceTCKTDO10 kΩV CC(2)(2)(2)(2)(2)nSTATUSCONF_DONEnCONFIGMSEL0MSEL1DATA0DCLKTMSTDIByteBlaster II, MasterBlaster, or ByteBlasterMV10-Pin Male Header(Top View)Pin 1V CC (1)GNDVIO (3)1 kΩGNDNotes to Figure 13–19:(1) You should connect the pull-up resistor to the same sup<strong>pl</strong>y voltage as the download cable.(2) You should connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG configuration scheme. If you onlyuse JTAG configuration, connect nCONFIG and MSEL0 to V CC , and MSEL1 to ground. Pull DATA0 and DCLK to highor low.(3) V IO is a reference voltage for the MasterBlaster output driver. V IO should match the device’s V CCIO . Refer to theMasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlaster MV, this pin is a noconnect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it is used for Active Serialprogramming; otherwise it is a no connect.(4) nCE must be connected to GND or driven low for successful configuration.GNDTo configure a single device in a JTAG chain, the programming software<strong>pl</strong>aces all other devices in bypass mode. In bypass mode, devices passprogramming data from the TDI pin to the TDO pin through a singlebypass register without being affected internally. This scheme enables theprogramming software to program or verify the target device.<strong>Configuration</strong> data driven into the device appears on the TDO pin oneclock cycle later.The Quartus II software verifies successful JTAG configuration uponcom<strong>pl</strong>etion. The software checks the state of CONF_DONE through theJTAG port. If CONF_DONE is not high, the Quartus II software indicatesthat configuration has failed. If CONF_DONE is high, the softwareindicates that configuration was successful. After the configuration bitstream is transmitted serially via the JTAG TDI port, the TCK port isclocked an additional 134 cycles to perform device initialization.Altera Corporation 13–33January 2007 Cyclone Device <strong>Handbook</strong>, Volume 1

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