12.07.2015 Views

Configuration Handbook - Kamami.pl

Configuration Handbook - Kamami.pl

Configuration Handbook - Kamami.pl

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Serial <strong>Configuration</strong> Device Memory Accesstimed erase cycle is in progress. The write in progress bit is 1 during theself-timed erase cycle and is 0 when it is com<strong>pl</strong>ete. The write enable latchbit in the status register is reset to 0 before the erase cycle is com<strong>pl</strong>ete.Figure 4–14. Erase Bulk Operation Timing DiagramnCS0 1 2 3 4 5 6 7DCLKOperation CodeASDIErase Sector OperationThe erase sector operation code is b'1101 1000, with the MSB listedfirst. The erase sector operation allows the user to erase a certain sector inthe serial configuration device by setting all bits inside the sector to 1 or0xFF. This operation is useful for users who access the unused sectors asgeneral purpose memory in their ap<strong>pl</strong>ications.The write enable operation must be executed prior to the erase sectoroperation so that the write enable latch bit in the status register is set to 1.The erase sector operation is im<strong>pl</strong>emented by first driving nCS low, thenshifting in the erase sector operation code and the three address bytes ofthe chosen sector on the ASDI pin. The three address bytes for the erasesector operation can be any address inside the specified sector. (SeeTables 4–9, 4–10, 4–11, and 4–12 for sector address range information.)Drive nCS high after the eighth bit of the erase sector operation code hasbeen latched in. Figure 4–15 shows the timing diagram.Immediately after the device drives nCS high, the self-timed erase sectorcycle is initiated. The self-timed erase sector cycle usually takes 2 s and isguaranteed to be less than 3 s for all serial configuration devices. Youmust account for this amount of delay before the memory contents can beaccessed. Alternatively, you can check the write in progress bit in thestatus register by executing the read status operation while the erase cycleis in progress. The write in progress bit is 1 during the self-timed erasecycle and is 0 when it is com<strong>pl</strong>ete. The write enable latch bit in the statusregister is reset to 0 before the erase cycle is com<strong>pl</strong>ete.4–30 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 2 April 2007

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!