Configuration Handbook - Kamami.pl

Device Configuration PinsTable 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 2 of 8)Pin NameUser ModeConfigurationSchemePin TypeDescriptionnIO_PULLUP N/A All Input Dedicated input that chooses whether theinternal pull-ups on the user I/Os and dualpurposeI/Os (DATA[7..0], nWS, nRS,RDYnBSY, nCS, CS, RUnLU, PGM[], CLKUSR,INIT_DONE, DEV_OE, DEV_CLR) are on oroff before and during configuration. A logic high(1.5-V, 1.8-V, 2.5-V, 3.3-V) turns off the weakinternal pull-ups, while a logic low turns themon.The nIO_PULLUP input buffer is powered byV CCINT and has an internal 2.5 kΩ pull-downresistor that is always active.MSEL[2..0] N/A All Input 3-bit configuration input that sets the Stratix orStratix GX device configuration scheme. SeeTable 11–2 for the appropriate connections.These pins can be connected to V CCIO of theI/O bank they reside in or ground. This pin usesSchmitt trigger input buffers.nCONFIG N/A All Input Configuration control input. Pulling this pin lowduring user-mode causes the FPGA to lose itsconfiguration data, enter a reset state, tri-stateall I/O pins. Returning this pin to a logic highlevel initiates a reconfiguration.If your configuration scheme uses anenhanced configuration device or EPC2device, nCONFIG can be tied directly to V CC orto the configuration device’s nINIT_CONFpin. This pin uses Schmitt trigger input buffers.11–52 Altera CorporationStratix Device Handbook, Volume 2 July 2005