Configuration Handbook - Kamami.pl

Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data SheetExternal flash interface programming is only allowed when theconfiguration controller has relinquished flash access (by tri-stating itsinternal interface). If the controller has not relinquished flash access(during configuration or JTAG-based ISP), you must hold the controllerin reset before initiating external programming. The controller can bereset by holding the FPGA nCONFIG line at a logic low level. This keepsthe controller in reset by holding the nSTATUS-OE line low, allowingexternal flash access.1 If initial programming of the enhanced configuration device isdone in-system via the external flash interface, the controllermust be kept in reset by driving the FPGA nCONFIG line low toprevent contention on the flash interface.Pin DescriptionTables 2–6 through 2–8 describe the enhanced configuration device pins.These tables include configuration interface pins, external flash interfacepins, JTAG interface pins, and other pins.Table 2–6. Configuration Interface PinsPin Name Pin Type DescriptionDATA[7..0] Output This is the configuration data output bus. DATA changes on each fallingedge of DCLK. DATA is latched into the FPGA on the rising edge of DCLK.DCLK Output The DCLK output pin from the enhanced configuration device serves asthe FPGA configuration clock. DATA is latched by the FPGA on the risingedge of DCLK.nCS Input The nCS pin is an input to the enhanced configuration device and isconnected to the FPGA’s CONF_DONE signal for error detection after allconfiguration data is transmitted to the FPGA. The FPGA will always drivenCS and OE low when nCONFIG is asserted. This pin contains aprogrammable internal weak pull-up resistor that can be disabled/enabledin the Quartus II software through the Disable nCS and OE pull-ups onconfiguration device option.Altera Corporation 2–21May 2007 Configuration Handbook, Volume 2