Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesFigure 11–16 shows the PPA configuration circuit. An optional addressdecoder controls the device’s nCS and CS pins. This decoder allows themicroprocessor to select the Stratix or Stratix GX device by accessing aparticular address, simplifying the configuration process.Figure 11–16. PPA Configuration CircuitV CC(1)10 kΩAddress DecoderADDRV CC (1)MemoryADDR DATA[7..0]10 kΩV CC(1)10 kΩStratix DeviceV CCMicroprocessorGNDnCSCSCONF_DONEnSTATUSnCEDATA[7..0]MSEL2MSEL1MSEL0nCEOGNDN.C.V CC(1)nWSnRSnCONFIG10 kΩRDYnBSYDCLKNote to Figure 11–16:(1) The pull-up resistor should be connected to the same supply voltage as the Stratix or Stratix GX device.The device’s nCS or CS pins can be toggled during PPA configuration ifthe design meets the specifications for t CSSU , t WSP , and t CSH given inTable 11–10 on page 11–36. The microprocessor can also directly controlthe nCS and CS signals. You can tie one of the nCS or CS signals to itsactive state (i.e., nCS may be tied low) and toggle the other signal tocontrol configuration.Stratix and Stratix GX devices can serialize data internally without themicroprocessor. When the Stratix or Stratix GX device is ready for thenext byte of configuration data, it drives RDYnBSY high. If themicroprocessor senses a high signal when it polls RDYnBSY, themicroprocessor strobes the next byte of configuration data into thedevice. Alternatively, the nRS signal can be strobed, causing theRDYnBSY signal to appear on DATA7. Because RDYnBSY does not need toAltera Corporation 11–31July 2005 Stratix Device Handbook, Volume 2