Configuration Handbook - Kamami.pl

Passive Serial & JTAGFigure 9–4. Combining JTAG Programming of Configuration Device & FPGA with PS Configuration of FPGAUsing a Configuration Device and Download Cable(1) VCC1 kΩVCC (1)1 kΩDownload Cable(JTAG Mode)10-Pin Male HeaderVCC (1) Download Cable(2) VCC (1)(PS Mode)10-Pin Male Header(2)VCC (1)(2)VCCVCCVIOVIOFPGAGNDGNDnMSELGND1 kΩ(3)(3)(3)(3)Configuration DeviceDATADCLKOEnCSTMSTCKTDInINIT_CONFTDO(3)DCLKCONF_DONEnCONFIGnSTATUSDATA0TDInCEOnCETRSTTMSTCKTDOGNDVCCN.C.Notes to Figure 9–4:(1) V CC should be connected to the same supply voltage as the configuration device. For APEX 20KE devices, nCONFIGshould be pulled up to V CCINT .(2) If the internal pull-up resistors of the configuration device are used, external pull-up resistors should not be usedon these pins.(3) To configure the FPGA with a download cable, you should either remove the configuration device from its socketor place a switch on the five common signals between the download cable and the configuration device.Figures 9–1 and 9–4 also apply for fast passive parallel (FPP) mode,except DATA[7..0] is connected from the enhanced configurationdevice to the FPGA(s) that supports FPP configuration. The MSEL pinsneed to be set accordingly.9–6 Altera CorporationConfiguration Handbook, Volume 2 April 2007