Configuration Handbook - Kamami.pl

More documents

Recommendations

Info

Board Layout Tips & Debugging Techniques101 Innovation DriveSan Jose, CA 95134www.altera.comPreliminary Information
11. Debugging ConfigurationProblemsCF52011-2.2IntroductionConfigurationReliabilityThis section provides information about how Altera ® FPGAs ensureconfiguration reliability and suggestions on laying out the configurationinterface on your board to avoid configuration problems. The last sectionprovides suggestions on debugging configuration issues.The architecture of Altera FPGAs have been designed to minimize theeffects of power supply and data noise in a system, and to ensure that theconfiguration data is not corrupted during configuration or normal usermodeoperation. A number of circuit design features are provided toensure the highest possible level of reliability from this SRAM technology.Cyclic redundancy code (CRC) circuitry is used to validate eachconfiguration data frame (sequence of data bits) as it is loaded into thetarget device. If the CRC calculated by the device does not match the CRCstored in the data frame, the configuration process is halted, and theFPGA drives the nSTATUS pin low to indicate an error has occurred. CRCcircuitry ensures that noisy systems will not cause errors that yield anincorrect or incomplete configuration.The device architecture also provides a very high level of reliability inlow-voltage brown-out conditions. The device’s SRAM cells require acertain voltage level to maintain accurate data. This voltage threshold issignificantly lower than the voltage required to activate the device's PORcircuitry. Therefore, the target device stops operating if the V CC starts tofail, and indicates an operation error by driving the nSTATUS pin low.The device must then be reconfigured before it can resume properoperation as a logic device. In configuration schemes where nCONFIG istied to V CC , reconfiguration begins as soon as V CC returns to an acceptablelevel. The low pulse on nSTATUS resets the configuration device bydriving OE low. In configuration schemes using an external host, thesystem must start the reconfiguration process by driving nCONFIG highafter the power supply returns to the minimum operating voltage.These device features ensure that Altera FPGAs have the highest possiblereliability in a wide variety of environments, and provide the same highlevel of system reliability that exists in other Altera PLDs.Altera Corporation 11–1April 2007
Page 1 and 2:
Configuration HandbookPreliminary I
Page 3 and 4:
ContentsVolume I...................
Page 5 and 6:
Altera FPGAsPreliminary Information
Page 7 and 8:
IntroductionAll configuration schem
Page 9 and 10:
Device Configuration Overview for P
Page 11 and 12:
Selecting a Configuration SchemeSel
Page 13 and 14:
Selecting a Configuration SchemePas
Page 15 and 16:
IntroductionfFor information on enh
Page 17 and 18:
Configuration FeaturesUse the data
Page 19 and 20:
Configuration FeaturesStratix III d
Page 21 and 22:
Configuration Features5. Select Add
Page 23 and 24:
Configuration FeaturesV CCPGM PinsS
Page 25 and 26:
Fast Passive Parallel Configuration
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Fast Active Serial Configuration (S
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Passive Serial ConfigurationPS Conf
Page 57 and 58:
Passive Serial ConfigurationAn opti
Page 59 and 60:
Passive Serial ConfigurationDCLK, D
Page 61 and 62:
Passive Serial ConfigurationFigure
Page 63 and 64:
Page 65 and 66:
Passive Serial Configuration1 To be
Page 67 and 68:
Passive Serial Configuration1 If yo
Page 69 and 70:
Passive Serial ConfigurationThe enh
Page 71 and 72:
Passive Serial ConfigurationThe Qua
Page 73 and 74:
Passive Serial Configuration1 You c
Page 75 and 76:
Passive Serial Configurationoption
Page 77 and 78:
Passive Serial ConfigurationIf you
Page 79 and 80:
JTAG ConfigurationJTAGConfiguration
Page 81 and 82:
JTAG ConfigurationFigure 11-29. JTA
Page 83 and 84:
JTAG ConfigurationTable 11-13. Dedi
Page 85 and 86:
JTAG ConfigurationAfter the first d
Page 87 and 88:
Device Configuration PinsTable 11-1
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
ConclusionConclusionDocumentRevisio
Page 99 and 100:
Introduction1 For more information
Page 101 and 102:
Configuration FeaturesTable 7-3. St
Page 103 and 104:
Configuration Features1 When using
Page 105 and 106:
Configuration Features6. Select the
Page 107 and 108:
Configuration FeaturesV CCPD PinsSt
Page 109 and 110:
Configuration Featuresthan 00X0 (MS
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Active Serial Configuration (Serial
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Passive Serial ConfigurationTable 7
Page 145 and 146:
Passive Serial ConfigurationfThe va
Page 147 and 148:
Passive Serial Configurationpulled
Page 149 and 150:
Passive Serial ConfigurationIf the
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Passive Serial Configurationsoftwar
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Passive Serial Configurationconfigu
Page 163 and 164:
Page 165 and 166:
Passive Serial ConfigurationUpon po
Page 167 and 168:
Passive Serial ConfigurationIn addi
Page 169 and 170:
Page 171 and 172:
Passive Parallel Asynchronous Confi
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
JTAG ConfigurationJTAGConfiguration
Page 183 and 184:
JTAG ConfigurationFigure 7-35. JTAG
Page 185 and 186:
JTAG ConfigurationTable 7-20. Dedic
Page 187 and 188:
JTAG ConfigurationAfter the first d
Page 189 and 190:
Device Configuration PinsDeviceConf
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
ConclusionConclusionDocumentRevisio
Page 205 and 206:
Device Configuration Overview■The
Page 207 and 208:
Device Configuration Overviewrelate
Page 209 and 210:
Configuration File SizeTDO & nCEO P
Page 211 and 212:
Configuration SchemesPS Configurati
Page 213 and 214:
Configuration SchemesFigure 11-2. S
Page 215 and 216:
Configuration SchemesRestart Config
Page 217 and 218:
Configuration SchemesTable 11-7 sho
Page 219 and 220:
Configuration SchemesFigure 11-6. M
Page 221 and 222:
Page 223 and 224:
Configuration SchemesTable 11-8. PS
Page 225 and 226:
Configuration SchemesFPP Configurat
Page 227 and 228:
Configuration SchemesDo not drive C
Page 229 and 230:
Configuration Schemesdefault, the I
Page 231 and 232:
Configuration SchemesFigure 11-13.
Page 233 and 234:
Configuration SchemesTable 11-9. FP
Page 235 and 236:
Configuration Schemesbe monitored,
Page 237 and 238:
Configuration SchemesPPA Configurat
Page 239 and 240:
Configuration SchemesTable 11-10 de
Page 241 and 242:
Configuration SchemesDuring JTAG co
Page 243 and 244:
Configuration SchemesJTAG-chain dev
Page 245 and 246:
Configuration SchemesfFor more info
Page 247 and 248:
Configuration SchemesProgram FlowTh
Page 249 and 250:
Configuration Schemessend JTAG data
Page 251 and 252:
Page 253 and 254:
Configuration SchemesTable 11-14. R
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Page 265 and 266:
Cyclone II Configuration OverviewTa
Page 267 and 268:
Configuration Data CompressionAltho
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
PS ConfigurationPS ConfigurationYou
Page 287 and 288:
PS ConfigurationConfiguration Stage
Page 289 and 290:
PS Configurationdevice also pulls n
Page 291 and 292:
PS ConfigurationYou must connect al
Page 293 and 294:
PS ConfigurationPS Configuration Ti
Page 295 and 296:
PS ConfigurationfAll information in
Page 297 and 298:
PS ConfigurationUpon power-up, the
Page 299 and 300:
PS ConfigurationnCONFIG is low and
Page 301 and 302:
PS ConfigurationFigure 13-14. Multi
Page 303 and 304:
PS ConfigurationnCONFIG low for at
Page 305 and 306:
PS ConfigurationDATA3, you can leav
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
PS ConfigurationPS Configuration Us
Page 313 and 314:
PS ConfigurationIn addition, becaus
Page 315 and 316:
PS Configurationthe five common sig
Page 317 and 318:
JTAG ConfigurationA device operatin
Page 319 and 320:
JTAG Configurationenables the progr
Page 321 and 322:
JTAG ConfigurationFigure 13-23. JTA
Page 323 and 324:
JTAG Configuration1 The Quartus II
Page 325 and 326:
JTAG Configurationfeature. To use t
Page 327 and 328:
Device Configuration PinsReconfigur
Page 329 and 330:
Page 331 and 332:
Page 333 and 334:
ConclusionTable 13-13 describes the
Page 335 and 336:
Document Revision HistoryDocumentRe
Page 337 and 338:
Device Configuration OverviewYou ca
Page 339 and 340:
Data CompressionWhen you enable com
Page 341 and 342:
Data CompressionCompression can als
Page 343 and 344:
Configuration SchemesConfigurationS
Page 345 and 346:
Configuration Schemesinternal oscil
Page 347 and 348:
Configuration SchemesFigure 13-6. C
Page 349 and 350:
Configuration SchemesFigure 13-7. C
Page 351 and 352:
Configuration SchemesASDI and nCS s
Page 353 and 354:
Configuration SchemesYou can progra
Page 355 and 356:
Configuration SchemesWhen configuri
Page 357 and 358:
Page 359 and 360:
Page 361 and 362:
Page 363 and 364:
Page 365 and 366:
Configuration SchemesFigure 13-18 s
Page 367 and 368:
Configuration Schemesattempt JTAG c
Page 369 and 370:
Configuration Schemes1 If V CCIO is
Page 371 and 372:
Page 373 and 374:
Configuration Schemes1 Both JTAG co
Page 375 and 376:
Configuration Schemessend JTAG data
Page 377 and 378:
Page 379 and 380:
Configuration SchemesTable 13-9. Re
Page 381 and 382:
Page 383 and 384:
Page 385 and 386:
Page 387 and 388:
Document Revision History13-52 Alte
Page 389 and 390:
Page 391 and 392:
Passive Serial Configurationinterna
Page 393 and 394:
Page 395 and 396:
Page 397 and 398:
Page 399 and 400:
Page 401 and 402:
Page 403 and 404:
Page 405 and 406:
Page 407 and 408:
Passive Serial ConfigurationHandsha
Page 409 and 410:
Passive Serial ConfigurationIf the
Page 411 and 412:
Page 413 and 414:
Passive Serial Configurationoption,
Page 415 and 416:
Page 417 and 418:
Page 419 and 420:
Page 421 and 422:
Page 423 and 424:
Page 425 and 426:
Page 427 and 428:
Page 429 and 430:
Page 431 and 432:
Page 433 and 434:
Page 435 and 436:
Page 437 and 438:
Page 439 and 440:
Page 441 and 442:
Page 443 and 444:
JTAG ConfigurationTable 6-6. PPA Ti
Page 445 and 446:
JTAG ConfigurationDuring JTAG confi
Page 447 and 448:
JTAG ConfigurationFigure 6-30. JTAG
Page 449 and 450:
Device Configuration PinsfFor more
Page 451 and 452:
Device Configuration PinsTable 6-9.
Page 453 and 454:
Page 455 and 456:
Device Configuration PinsJTAG pins
Page 457 and 458:
IntroductionTable 7-2 shows the app
Page 459 and 460:
Page 461 and 462:
Passive Serial Configuration1 V CCI
Page 463 and 464:
Passive Serial ConfigurationWhen CO
Page 465 and 466:
Passive Serial ConfigurationfFor mo
Page 467 and 468:
Page 469 and 470:
Page 471 and 472:
Page 473 and 474:
Page 475 and 476:
Page 477 and 478:
Passive Serial Configurationpulled
Page 479 and 480:
Page 481 and 482:
Passive Serial ConfigurationYou can
Page 483 and 484:
Page 485 and 486:
Passive Serial ConfigurationYou can
Page 487 and 488:
Page 489 and 490:
Passive Parallel Synchronous Config
Page 491 and 492:
Page 493 and 494:
Page 495 and 496:
Page 497 and 498:
Page 499 and 500:
Page 501 and 502:
Page 503 and 504:
Page 505 and 506:
Page 507 and 508:
JTAG ConfigurationTable 7-6. PPA Ti
Page 509 and 510:
JTAG Configurationprogramming devic
Page 511 and 512:
JTAG ConfigurationJTAG-chain device
Page 513 and 514:
JTAG ConfigurationThe Jam Player pr
Page 515 and 516:
Page 517 and 518:
Page 519 and 520:
Page 521 and 522:
APEX 20KE Power SequencingThese gui
Page 523 and 524:
APEX 20KE Power SequencingUse these
Page 525 and 526:
APEX 20KE Power Sequencing7-70 Alte
Page 527 and 528:
Introductionsuccessfully. Toggling
Page 529 and 530:
Passive Serial ConfigurationThe fol
Page 531 and 532:
Passive Serial ConfigurationUpon po
Page 533 and 534:
Page 535 and 536:
Page 537 and 538:
Page 539 and 540:
Page 541 and 542:
Page 543 and 544:
Page 545 and 546:
Page 547 and 548:
Page 549 and 550:
Passive Serial ConfigurationIn mult
Page 551 and 552:
Page 553 and 554:
Page 555 and 556:
Page 557 and 558:
Page 559 and 560:
Page 561 and 562:
Page 563 and 564:
Page 565 and 566:
Page 567 and 568:
Page 569 and 570:
Page 571 and 572:
Page 573 and 574:
Page 575 and 576:
Page 577 and 578:
Page 579 and 580:
Page 581 and 582:
Page 583 and 584:
JTAG ConfigurationTable 8-18 explai
Page 585 and 586:
JTAG ConfigurationMercury, APEX 20K
Page 587 and 588:
JTAG ConfigurationOther Altera devi
Page 589 and 590:
Page 591 and 592:
Page 593 and 594:
Page 595 and 596:
Device Configuration Pins8-70 Alter
Page 597 and 598:
FPGA Configuration DevicesPrelimina
Page 599 and 600:
Choosing a Configuration DevicefFor
Page 601 and 602:
1-4 Altera CorporationConfiguration
Page 603 and 604:
1-6 Altera CorporationConfiguration
Page 605 and 606:
Document Revision HistoryDocumentRe
Page 607 and 608:
Functional Description■■■■
Page 609 and 610:
Functional DescriptionFigure 2-1. E
Page 611 and 612:
Functional DescriptionIn addition t
Page 613 and 614:
Functional DescriptionFast Passive
Page 615 and 616:
Functional DescriptionThe configura
Page 617 and 618:
Functional DescriptionTable 2-3 sum
Page 620 and 621:
Enhanced Configuration Devices (EPC
Page 622 and 623:
Page 624 and 625:
Page 626 and 627:
Page 628 and 629:
Page 630 and 631:
Page 632 and 633:
Page 634 and 635:
Page 636 and 637:
Page 638 and 639:
Page 640 and 641:
Page 642 and 643:
Page 644 and 645:
3. Altera EnhancedConfiguration Dev
Page 646 and 647:
Altera Enhanced Configuration Devic
Page 648 and 649:
Page 650 and 651:
Page 652 and 653:
Page 654 and 655:
Page 656 and 657:
Page 658 and 659:
Page 660 and 661:
Page 662 and 663:
Page 664 and 665:
Page 666 and 667:
4. Serial ConfigurationDevices (EPC
Page 668 and 669:
Serial Configuration Devices (EPCS1
Page 670 and 671:
Page 672 and 673:
Page 674 and 675:
Page 676 and 677:
Page 678 and 679:
Page 680 and 681:
Page 682 and 683:
Page 684 and 685:
Page 686 and 687:
Page 688 and 689:
Page 690 and 691:
Page 692 and 693:
Page 694 and 695:
Page 696 and 697:
Page 698 and 699:
Page 700 and 701:
Page 702 and 703:
Page 704 and 705:
Page 706 and 707:
Page 708 and 709:
5. Configuration Devices forSRAM-Ba
Page 710 and 711:
Configuration Devices for SRAM-Base
Page 712 and 713:
Page 714 and 715:
Page 716 and 717:
Page 718 and 719:
Page 720 and 721:
Page 722 and 723:
Page 724 and 725:
Page 726 and 727:
Page 728 and 729:
Page 730 and 731:
Page 732 and 733:
Page 734 and 735:
Page 736 and 737:
Page 738 and 739: Configuration Devices for SRAM-Base
Page 740 and 741: Configuration Devices for SRAM-Base
Page 742 and 743: Software SettingsPreliminary Inform
Page 744 and 745: IntroductionThe Configuration schem
Page 746 and 747: IntroductionFigure 6-3. Configurati
Page 748 and 749: IntroductionTable 6-1. Configuratio
Page 750 and 751: IntroductionTable 6-1. Configuratio
Page 752 and 753: Document Revision HistoryDocumentRe
Page 754 and 755: Generating Configuration FilesYou c
Page 756 and 757: SRAM Object File (.sof)6. Click on
Page 758 and 759: Tabular Text File (.ttf)Tabular Tex
Page 760 and 761: Document Revision History7-8 Altera
Page 762 and 763: 8. Configuring Mixed AlteraFPGA Cha
Page 764 and 765: Configuring Mixed Altera FPGA Chain
Page 766 and 767: 9. Combining DifferentConfiguration
Page 768 and 769: Combining Different Configuration S
Page 774 and 775: 10. Using Flash Memory toConfigure
Page 776 and 777: Using Flash Memory to Configure FPG
Page 790 and 791: Board Layout TipsBoard LayoutTipsEv
Page 792 and 793: Debugging Suggestions■■To check
Page 794 and 795: Debugging SuggestionsUsing JTAG Con
Page 796: Document Revision History11-8 Alter
show all

Configuration Handbook - Kamami.pl

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?