Configuration Handbook - Kamami.pl

Configuring Stratix III DevicesTable 11–10. PS Timing Parameters for Stratix III Devices Note (1) (Part 2 of 2)Symbol Parameter Minimum Maximum Unitst CH DCLK high time 4 — nst CL DCLK low time 4 — nst CLK DCLK period 10 — nsf MAX DCLK frequency — 100 MHzt R Input rise time — 40 nst Input fall time — 40 nst CD2UM CONF_DONE high to user mode (3) 20 100 μst CD2CU CONF_DONE high to CLKUSR enabled 4 × maximumDCLK period— —t CD2UMCCONF_DONE high to user mode withCLKUSR option ont CD2CU + (4,436 ×CLKUSR period)— —Notes to Table 11–10:(1) This information is preliminary.(2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.(3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for startingthe device.fDevice configuration options and how to create configuration files arediscussed further in the Software Settings chapter in volume 2 of theConfiguration Handbook.An example PS design that uses a MAX II device as the external host forconfiguration will be available when the devices are available.PS Configuration Using a MicroprocessorIn this PS configuration scheme, a microprocessor can control the transferof configuration data from a storage device, such as flash memory, to thetarget Stratix III device.fAll information in the “PS Configuration Using a MAX II Device as anExternal Host” section is also applicable when using a microprocessor asan external host. Refer to that section for all configuration and timinginformation.Altera Corporation 11–49May 2007 Stratix III Device Handbook, Volume 1