Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesTable 7–24 describes the dedicated JTAG pins. JTAG pins must be keptstable before and during configuration to prevent accidental loading ofJTAG instructions. The TDI, TMS, and TRST have weak internal pull-upresistors (typically 25 kΩ) while TCK has a weak internal pull-downresistor. If you plan to use the SignalTap embedded logic array analyzer,you need to connect the JTAG pins of the Stratix II or Stratix II GX deviceto a JTAG header on your board.Table 7–24. Dedicated JTAG PinsPin Name User Mode Pin TypeDescriptionTDI N/A Input Serial input pin for instructions as well as test and programming data. Datais shifted in on the rising edge of TCK. The TDI pin is powered by the 3.3-VV CCPD supply.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting this pin to V CC .TDO N/A Output Serial data output pin for instructions as well as test and programming data.Data is shifted out on the falling edge of TCK. The pin is tri-stated if data isnot being shifted out of the device. The TDO pin is powered by V CCIO in I/Obank 4. For recommendations on connecting a JTAG chain with multiplevoltages across the devices in the chain, refer to the chapter IEEE 1149.1(JTAG) Boundary Scan Testing in Stratix II & Stratix II GX Devices in volume2 of the Stratix II Handbook or the Stratix II GX Device Handbook.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by leaving this pin unconnected.TMS N/A Input Input pin that provides the control signal to determine the transitions of theTAP controller state machine. Transitions within the state machine occur onthe rising edge of TCK. Therefore, TMS must be set up before the risingedge of TCK. TMS is evaluated on the rising edge of TCK. The TMS pin ispowered by the 3.3-V V CCPD supply.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting this pin to V CC .TCK N/A Input The clock input to the BST circuitry. Some operations occur at the risingedge, while others occur at the falling edge. The TCK pin is powered by the3.3-V V CCPD supply.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting TCK to GND.TRST N/A Input Active-low input to asynchronously reset the boundary-scan circuit. TheTRST pin is optional according to IEEE Std. 1149.1. The TRST pin ispowered by the 3.3-V V CCPD supply.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting the TRST pin to GND.Altera Corporation 7–105May 2007 Stratix II Device Handbook, Volume 2