Configuration Handbook - Kamami.pl

Passive Serial ConfigurationTable 8–9. PS Timing Parameters for ACEX & FLEX 10KE DevicesSymbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 200 nst CF2ST0 nCONFIG low to nSTATUS low 200 nst CFG nCONFIG low pulse width 2 µst STATUS nSTATUS low pulse width 1 10 (1) µst CF2ST1 nCONFIG high to nSTATUS high 4 (1) µst CF2CK nCONFIG high to first rising edge on DCLK 5 µst ST2CK nSTATUS high to first rising edge on DCLK 1 µst DSU Data setup time before rising edge on DCLK 10 nst DH Data hold time after rising edge on DCLK 0 nst CH DCLK high time 15 nst CL DCLK low time 15 nst CLK DCLK period 30 nsf MAX DCLK maximum frequency 33.3 MHzt CD2UM CONF_DONE high to user mode (2) 0.6 2 µsNotes to Table 8–9:(1) This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.(2) The minimum and maximum numbers apply only if DCLK is chosen as the clock source for starting up the device.If the clock source is CLKUSR, multiply the clock period by 10 to obtain this value.Table 8–10. PS Timing Parameters for FLEX 10K Devices (Part 1 of 2)Symbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 200 nst CF2ST0 nCONFIG low to nSTATUS low 200 nst CFG nCONFIG low pulse width 2 µst STATUS nSTATUS low pulse width 1 10 (1) µst CF2ST1 nCONFIG high to nSTATUS high 4 (1) µst CF2CK nCONFIG high to first rising edge on DCLK 5 µst ST2CK nSTATUS high to first rising edge on DCLK 1 µst DSU Data setup time before rising edge on DCLK 10 nst DH Data hold time after rising edge on DCLK 0 nst CH DCLK high time 30 nst CL DCLK low time 30 nst CLK DCLK period 60 ns8–28 Altera CorporationConfiguration Handbook, Volume 1 August 2005