Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesFigure 7–37 shows JTAG configuration of a Stratix II or Stratix II GXdevice with a microprocessor.Figure 7–37. JTAG Configuration of a Single Device Using a MicroprocessorV CC (1)MemoryADDR DATAMicroprocessorV CCStratix II DeviceTRSTTDITCKTMSTDOnSTATUSCONF_DONEnCONFIGMSEL[3..0]nCEO(3) nCEV CC (1)1 kΩ(2)(2)N.C.GND1 kΩNotes to Figure 7–37:(1) The pull-up resistor should be connected to a supply that provides an acceptableinput signal for all devices in the chain. V CC should be high enough to meet the V IHspecification of the I/O on the device.(2) The nCONFIG, MSEL[3..0] pins should be connected to support a non-JTAGconfiguration scheme. If only JTAG configuration is used, connect nCONFIG toV CC , and MSEL[3..0] to ground. Pull DCLK either high or low, whichever isconvenient on your board.(3) nCE must be connected to GND or driven low for successful JTAG configuration.Jam STAPLJam STAPL, JEDEC standard JESD-71, is a standard file format forin-system programmability (ISP) purposes. Jam STAPL supportsprogramming or configuration of programmable devices and testing ofelectronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is afreely licensed open standard.The Jam Player provides an interface for manipulating the IEEE Std.1149.1 JTAG TAP state machine.fFor more information on JTAG and Jam STAPL in embeddedenvironments, refer to AN 122: Using Jam STAPL for ISP & ICR via anEmbedded Processor. To download the jam player, visit the Altera web siteat www.altera.com.Altera Corporation 7–91May 2007 Stratix II Device Handbook, Volume 2