Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationThe APEX II device receives configuration data on its DATA[7..0] pinsand the clock is received on the DCLK pin. Data is latched into the FPGAon the rising edge of DCLK. Data is continuously clocked into the targetdevice until CONF_DONE goes high. After the FPGA has received allconfiguration data successfully, it releases the open-drain CONF_DONEpin, which is pulled high by an external 1-kΩ pull-up resistor. A low-tohightransition on CONF_DONE indicates configuration is complete andinitialization of the device can begin.In APEX II devices, the initialization clock source is either the APEX IIinternal oscillator (typically 10 MHz) or the optional CLKUSR pin. Bydefault, the internal oscillator is the clock source for initialization. If theinternal oscillator is used, the APEX II device will take care to provideitself with enough clock cycles for proper initialization. Therefore, if theinternal oscillator is the initialization clock source, sending the entireconfiguration file to the device is sufficient to configure and initialize thedevice. Driving DCLK to the device after configuration is complete doesnot affect device operation.You also have the flexibility to synchronize initialization of multipledevices by using the CLKUSR option. The Enable user-supplied start-up clock(CLKUSR) option can be turned on in the Quartus II software from theGeneral tab of the Device & Pin Options dialog box. Supplying a clockon CLKUSR will not affect the configuration process. After allconfiguration data has been accepted and CONF_DONE goes high,APEX II devices require 40 clock cycles to initialize properly.An optional INIT_DONE pin is available, which signals the end ofinitialization and the start of user-mode with a low-to-high transition.This Enable INIT_DONE output option is available in the Quartus IIsoftware from the General tab of the Device & Pin Options dialog box.If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullupresistor when nCONFIG is low and during the beginning ofconfiguration. Once the option bit to enable INIT_DONE is programmedinto the device (during the first frame of configuration data), theINIT_DONE pin will go low. When initialization is complete, theINIT_DONE pin will be released and pulled high. The microprocessormust be able to detect this low-to-high transition which signals the FPGAhas entered user mode. In user-mode, the user I/O pins will no longerhave weak pull-ups and will function as assigned in your design. Wheninitialization is complete, the FPGA enters user mode.6–40 Altera CorporationConfiguration Handbook, Volume 1 August 2005