Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX Devices1 The TDO output is powered by the V CCIO power supply of I/Obank 4. For recommendations on how to connect a JTAG chainwith multiple voltages across the devices in the chain, refer tothe IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix II &Stratix II GX Devices chapter in volume 2 of the Stratix II DeviceHandbook or the Stratix II GX Device Handbook.Table 7–19. Dedicated JTAG PinsPin Name Pin Type DescriptionTDI Test data input Serial input pin for instructions as well as test and programming data. Data isshifted in on the rising edge of TCK. If the JTAG interface is not required on theboard, the JTAG circuitry can be disabled by connecting this pin to V CC .TDO Test data output Serial data output pin for instructions as well as test and programming data. Datais shifted out on the falling edge of TCK. The pin is tri-stated if data is not beingshifted out of the device. If the JTAG interface is not required on the board, theJTAG circuitry can be disabled by leaving this pin unconnected.TMS Test mode select Input pin that provides the control signal to determine the transitions of the TAPcontroller state machine. Transitions within the state machine occur on the risingedge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMSis evaluated on the rising edge of TCK. If the JTAG interface is not required onthe board, the JTAG circuitry can be disabled by connecting this pin to V CC .TCK Test clock input The clock input to the BST circuitry. Some operations occur at the rising edge,while others occur at the falling edge. If the JTAG interface is not required on theboard, the JTAG circuitry can be disabled by connecting this pin to GND.TRSTTest reset input(optional)Active-low input to asynchronously reset the boundary-scan circuit. The TRSTpin is optional according to IEEE Std. 1149.1. If the JTAG interface is not requiredon the board, the JTAG circuitry can be disabled by connecting this pin to GND.During JTAG configuration, data can be downloaded to the device on thePCB through the USB Blaster, MasterBlaster, ByteBlaster II, orByteBlasterMV download cable. Configuring devices through a cable issimilar to programming devices in-system, except the TRST pin should beconnected to V CC . This ensures that the TAP controller is not reset.Figure 7–35 shows JTAG configuration of a single Stratix II orStratix II GX device.Altera Corporation 7–85May 2007 Stratix II Device Handbook, Volume 2