Configuration Handbook - Kamami.pl

Device Configuration OverviewYou can select a Cyclone FPGA configuration scheme by driving itsMSEL1 and MSEL0 pins either high (1) or low (0), as shown in Table 13–2.If your application only requires a single configuration mode, the MSELpins can be connected to V CC (the I/O bank’s V CCIO voltage where theMSEL pin resides) or to ground. If your application requires more thanone configuration mode, the MSEL pins can be switched after the FPGAhas been configured successfully. Toggling these pins during user modedoes not affect the device operation. However, the MSEL pins must bevalid before initiating reconfiguration.Table 13–2. Selecting Cyclone Configuration SchemesMSEL1 MSEL0 Configuration Scheme0 0 AS0 1 PS0 1 JTAG-based (1)Note to Table 13–2:(1) JTAG-based configuration takes precedence over other schemes, which meansthat MSEL pin settings are ignored.After configuration, Cyclone FPGAs will initialize registers and I/O pins,then enter user mode and function as per the user design. Figure 13–1shows an AS configuration waveform.Figure 13–1. AS Configuration WaveformnCONFIGnSTATUSCONF_DONEnCSODCLKASDORead AddressDATA0bit N bit N − 1bit 1 bit 0136 CyclesINIT_DONEUser I/OUser ModeTri-stated with internalpull-up resistor.13–2 Altera CorporationCyclone Device Handbook, Volume 1 January 2007