Configuration Handbook - Kamami.pl

Configuring APEX 20KE & APEX 20KC DevicesA device operating in JTAG mode uses four required pins, TDI, TDO, TMS,and TCK, and one optional pin, TRST. All user I/O pins are tri-statedduring JTAG configuration. APEX 20KE and APEX 20KC devices aredesigned such that JTAG instructions have precedence over any deviceconfiguration modes. This means that JTAG configuration can take placewithout waiting for other configuration modes to complete. For example,if you attempt JTAG configuration of APEX 20KE and APEX 20KC FPGAsduring PS configuration, PS configuration will be terminated and JTAGconfiguration will begin.Table 7–7 explains each JTAG pin’s function.Table 7–7. JTAG Pin DescriptionsPin Description FunctionTDI Test data input Serial input pin for instructions as well as test and programming data.Data is shifted in on the rising edge of TCK.If the JTAG interface is not required on the board, the JTAG circuitry canbe disabled by connecting this pin to V CC .TDO Test data output Serial data output pin for instructions as well as test and programmingdata. Data is shifted out on the falling edge of TCK. The pin is tri-statedif data is not being shifted out of the device.If the JTAG interface is not required on the board, the JTAG circuitry canbe disabled by leaving this pin unconnected.TMS Test mode select Input pin that provides the control signal to determine the transitions ofthe TAP controller state machine. Transitions within the state machineoccur on the rising edge of TCK. Therefore, TMS must be set up beforethe rising edge of TCK. TMS is evaluated on the rising edge of TCK.If the JTAG interface is not required on the board, the JTAG circuitry canbe disabled by connecting this pin to V CC .TCK Test clock input The clock input to the BST circuitry. Some operations occur at the risingedge, while others occur at the falling edge.If the JTAG interface is not required on the board, the JTAG circuitry canbe disabled by connecting this pin to GND.TRST Test reset input (optional) Active-low input to asynchronously reset the boundary-scan circuit. TheTRST pin is optional according to IEEE Std. 1149.1.If the JTAG interface is not required on the board, the JTAG circuitry canbe disabled by connecting this pin to GND.1 If V CCIO of the bank where the JTAG pins reside, are tied to3.3-V, both the I/O pins and JTAG TDO port will drive at 3.3-Vlevels.During JTAG configuration, data can be downloaded to the device on thePCB through the USB Blaster, MasterBlaster, ByteBlaster II, orByteBlasterMV header. Configuring devices through a cable is similar toAltera Corporation 7–53August 2005 Configuration Handbook, Volume 1