Configuration Handbook - Kamami.pl

Configuration Devices for SRAM-Based LUT Devices Data SheetPin InformationfTable 5–20 describes EPC2, EPC1, and EPC1441 pin functions duringdevice configuration.For pin information on enhanced configuration devices, refer to theEnhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet. For pininformation on serial configuration devices, refer to the SerialConfiguration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet.Table 5–20. EPC2, EPC1 & EPC1441 Pin Functions During Configuration (Part 1 of 4)Pin Name8-PinPDIP (1)Pin Number20-PinPLCC32-PinTQFP (2)Pin TypeDescriptionDATA 1 2 31 Output Serial data output. The DATA pin connects to theDATA0 of the FPGA. DATA is latched into theFPGA on the rising edge of DCLK.The DATA pin is tri-stated before configurationand when the nCS pin is high. Afterconfiguration, the EPC2 device will drive DATAhigh, while the EPC1 and EPC1441 device willtri-state DATA.DCLK 2 4 2 Bidirectional Clock output when configuring with a singleconfiguration device or when the configurationdevice is the first (master) device in a chain.Clock input for the next (slave) configurationdevices in a chain. The DCLK pin connects to theDCLK of the FPGA.Rising edges on DCLK increment the internaladdress counter and present the next bit of dataon the DATA pin. The counter is incrementedonly if the OE input is held high, the nCS input isheld low, and all configuration data has not beentransferred to the target device.After configuration or when OE is low, the EPC2,EPC1 and EPC1441 device will drive DCLK low.Altera Corporation 5–27April 2007 Configuration Handbook, Volume 2