Configuration Handbook - Kamami.pl

Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K DevicesAfter the FPGA has received all configuration data successfully, it releasesthe open-drain CONF_DONE pin, which is pulled high by a pull-upresistor. Since CONF_DONE is tied to the configuration device’s nCS pin,the configuration device is disabled when CONF_DONE goes high.Enhanced configuration and EPC2 devices have an optional internal pullupresistor on the nCS pin. This option is available in the Quartus IIsoftware from the General tab of the Device & Pin Options dialog box.If this internal pull-up is not used, an external 1-kΩ pull-up resistor on thenCS/CONF_DONE line is required. A low-to-high transition onCONF_DONE indicates configuration is complete and initialization of thedevice can begin.In Mercury and APEX 20K (2.5 V) devices, the initialization clock sourceis either the FPGA’s internal oscillator (typically 10 MHz) or the optionalCLKUSR pin. By default, the internal oscillator is the clock source forinitialization. If the internal oscillator is used, the Mercury or APEX 20K(2.5 V) device will allow enough clock cycles for proper initialization.In ACEX 1K and FLEX 10K devices, the initialization clock source is eitheran external host (e.g. a configuration device or microprocessor) or theoptional CLKUSR pin. By default, an external host must provide theinitialization clock on the DCLK pin. Programming files generated by theQuartus II or MAX+PLUS II software already have these initializationclock cycles included in the file.You also have the flexibility to synchronize initialization of multipledevices by using the CLKUSR option. You can turn on the Enable usersuppliedstart-up clock (CLKUSR) option in the Quartus II software fromthe General tab of the Device & Pin Options dialog box. Supplying aclock on CLKUSR will not affect the configuration process. After allconfiguration data has been accepted and CONF_DONE goes high,Mercury devices require 136 clock cycles to initialize properly, APEX 20K(2.5 V) devices require 40 clock cycles, ACEX 1K and FLEX 10K devicesrequire 10 clock cycles.Altera Corporation 8–7August 2005 Configuration Handbook, Volume 1