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Configuration Handbook - Kamami.pl

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Configuring Cyclone II DevicesTable 13–12 describes the optional configuration pins. If these optionalconfiguration pins are not enabled in the Quartus II software, they areavailable as general-purpose user I/O pins. Therefore duringconfiguration, these pins function as user I/O pins and are tri-stated withweak pull-up resistors.Table 13–12. Optional <strong>Configuration</strong> PinsPin Name User Mode Pin Type DescriptionCLKUSR N/A if option ison. I/O if optionis off.InputThis is an optional user-sup<strong>pl</strong>ied clock input thatsynchronizes the initialization of one or more devices. Thispin is enabled by turning on the Enable user-sup<strong>pl</strong>iedstart-up clock (CLKUSR) option in the Quartus II softwareINIT_DONEDEV_OEDEV_CLRnN/A if option ison. I/O if optionis off.N/A if option ison. I/O if optionis off.N/A if option ison. I/O if optionis off.Output opendrainInputInputThis is a status pin that can be used to indicate when thedevice has initialized and is in user mode. When nCONFIGis low and during the beginning of configuration, theINIT_DONE pin is tri-stated and pulled high due to anexternal 10-kΩ pull-up resistor. Once the option bit toenable INIT_DONE is programmed into the device (duringthe first frame of configuration data), the INIT_DONE pingoes low. When initialization is com<strong>pl</strong>ete, the INIT_DONEpin is released and pulled high and the FPGA enters usermode. Thus, the monitoring circuitry must be able to detecta low-to-high transition. This pin is enabled by turning onthe Enable INIT_DONE output option in the Quartus IIsoftware.Optional pin that allows the user to override all tri-states onthe device. When this pin is driven low, all I/O pins are tristated.When this pin is driven high, all I/O pins behave asprogrammed. This pin is enabled by turning on the Enabledevice-wide output enable (DEV_OE) option in theQuartus II software.Optional pin that allows you to override all clears on alldevice registers. When this pin is driven low, all registersare cleared. When this pin is driven high, all registersbehave as programmed. This pin is enabled by turning onthe Enable device-wide reset (DEV_CLRn) option in theQuartus II software.Altera Corporation 13–69February 2007 Cyclone II Device <strong>Handbook</strong>, Volume 1

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