Configuration Handbook - Kamami.pl

Configuration Devices for SRAM-Based LUT Devices Data SheetFigure 5–4. EPC2 JTAG WaveformsTMSTDIt JCPt JCHt JCLt JPSUTCKt JPZX t JPCOt JPHt JPXZTDOSignalto beCapturedSignalto beDrivent JSZXt JSSU t JSHt JSCO t JSXZTable 5–7 shows the timing parameters and values for configurationdevices.Table 5–7. JTAG Timing Parameters & ValuesSymbol Parameter Min Max Unitt JCP TCK clock period 100 nst JCH TCK clock high time 50 nst JCL TCK clock low time 50 nst JPSU JTAG port setup time 20 nst JPH JTAG port hold time 45 nst JPCO JTAG port clock to output 25 nst JPZX JTAG port high impedance to valid output 25 nst JPXZ JTAG port valid output to high impedance 25 nst JSSU Capture register setup time 20 nst JSH Capture register hold time 45 nst JSCO Update register clock to output 25 nst JSZX Update register high-impedance to valid output 25 nst JSXZ Update register valid output to high impedance 25 nsAltera Corporation 5–19April 2007 Configuration Handbook, Volume 2