Configuration Handbook - Kamami.pl

Serial Configuration Device Memory AccessFigure 4–6. Write Disable Operation Timing DiagramnCS0 1 2 3 4 5 6 7DCLKOperation CodeASDIDATAHigh ImpedanceRead Status OperationThe read status operation code is b'0000 0101, with the MSB listed first.You can use the read status operation to read the status register.Figures 4–7 and 4–8 show the status bits in the status register of bothserial configuration devices.Figure 4–7. EPCS4, EPCS16, and EPCS64 Status Register Status BitsBit 7 Bit 0BP2 BP1 BP0 WEL WIPBlock Protect Bits [2..0]Write InProgress BitWrite EnableLatch BitFigure 4–8. EPCS1 Status Register Status BitsBit 7 Bit 0BP1 BP0 WEL WIPBlock ProtectBits [1..0]Write InProgress BitWrite EnableLatch Bit4–22 Altera CorporationConfiguration Handbook, Volume 2 April 2007