Configuration Handbook - Kamami.pl

Configuring APEX II DevicesFigure 6–20. Single Device FPP Configuration Using a MicroprocessorMemoryADDRDATA[7..0]V CC (1)V CC (1)1 kΩ 1 kΩAPEX II DeviceV CCMicroprocessorGNDCONF_DONEnSTATUSnCEDATA[7..0]MSEL1MSEL0nCEOGNDN.C.nCONFIGDCLKNote to Figure 6–20:(1) The pull-up resistor should be connected to a supply that provides an acceptableinput signal for the device.Upon power-up, the APEX II device goes through a Power-On Reset(POR) for approximately 5 µs. During POR, the device resets and holdsnSTATUS low, and tri-states all user I/O pins. Once the FPGAsuccessfully exits POR, all user I/O pins are tri-stated. APEX II deviceshave weak pull-up resistors on the user I/O pins which are on before andduring configuration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the APEX II Programmable Logic Device Family Data Sheet.The configuration cycle consists of three stages: reset, configuration andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration, the microprocessor must generate a low-to-hightransition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configuration,and JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 1-kΩpull-up resistor. Once nSTATUS is released, the FPGA is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS ispulled high, the microprocessor should place the configuration data onebyte at a time on the DATA[7..0] pins.Altera Corporation 6–39August 2005 Configuration Handbook, Volume 1