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Configuration Handbook - Kamami.pl

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Serial <strong>Configuration</strong> Device Memory AccessFigure 4–12. Read Silicon ID Operation Timing DiagramnCSDCLK0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39Operation CodeThree Dummy BytesASDI23 22 21 3 2 1 0DATAHigh ImpedanceMSBSilicon ID7 6 5 4 3 2 1 0MSBWrite Bytes OperationThe write bytes operation code is b'0000 0010, with the MSB listedfirst. The write bytes operation allows bytes to be written to the memory.The write enable operation must be executed prior to the write bytesoperation to set the write enable latch bit in the status register to 1.The write bytes operation is im<strong>pl</strong>emented by driving nCS low, followedby the write bytes operation code, three address bytes and a minimumone data byte on ASDI. If the eight least significant address bits(A[7..0]) are not all 0, all sent data that goes beyond the end of thecurrent page is not written into the next page. Instead, this data is writtenat the start address of the same page (from the address whose eight LSBsare all 0). Drive nCS low during the entire write bytes operation sequenceas shown in Figure 4–13.If more than 256 data bytes are shifted into the serial configuration devicewith a write bytes operation, the previously latched data is discarded andthe last 256 bytes are written to the page. However, if less than 256 databytes are shifted into the serial configuration device, they are guaranteedto be written at the specified addresses and the other bytes of the samepage are unaffected.If the design must write more than 256 data bytes to the memory, it needsmore than one page of memory. Send the write enable and write bytesoperation codes followed by three new targeted address bytes and256 data bytes before a new page is written.nCS must be driven high after the eighth bit of the last data byte has beenlatched in. Otherwise, the device will not execute the write bytesoperation. The write enable latch bit in the status register is reset to 0before the com<strong>pl</strong>etion of each write bytes operation. Therefore, the writeenable operation must be carried out before the next write bytesoperation.4–28 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 2 April 2007

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