Configuration Handbook - Kamami.pl

Configuring Stratix III Devices1 V CC , V CCIO , V CCPGM and V CCPD , of the banks where theconfiguration and JTAG pins reside, need to be fully powered tothe appropriate voltage levels in order to begin theconfiguration process.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 10-kΩpull-up resistor. Once nSTATUS is released, the device is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS ispulled high, the MAX II device should place the configuration data onebit at a time on the DATA0 pin. If you are using configuration data in .rbf,.hex, or .ttf format, you must send the least significant bit (LSB) of eachdata byte first. For example, if the RBF contains the byte sequence 02 1BEE 01 FA, the serial bitstream you should transmit to the device is0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.The Stratix III device receives configuration data on the DATA0 pin andthe clock is received on the DCLK pin. Data is latched into the device onthe rising edge of DCLK. Data is continuously clocked into the targetdevice until CONF_DONE goes high. After the device has received allconfiguration data successfully, it releases the open-drain CONF_DONEpin, which is pulled high by an external 10-kΩ pull-up resistor. Alow-to-high transition on CONF_DONE indicates configuration is completeand initialization of the device can begin. The CONF_DONE pin must havean external 10-kΩ pull-up resistor in order for the device to initialize.In Stratix III devices, the initialization clock source is either the internaloscillator (typically 10 MHz) or the optional CLKUSR pin. By default, theinternal oscillator is the clock source for initialization. If you use theinternal oscillator, the Stratix III device provides itself with enough clockcycles for proper initialization. Therefore, if the internal oscillator is theinitialization clock source, sending the entire configuration file to thedevice is sufficient to configure and initialize the device. Driving DCLK tothe device after configuration is complete does not affect deviceoperation.You also have the flexibility to synchronize initialization of multipledevices or to delay initialization with the CLKUSR option. You can turn onthe Enable user-supplied start-up clock (CLKUSR) option in theQuartus II software from the General tab of the Device and Pin Optionsdialog box. If you supply a clock on CLKUSR, it will not affect theconfiguration process. After all configuration data has been accepted andCONF_DONE goes high, CLKUSR will be enabled after the time specified ast CD2CU . After this time period elapses, Stratix III devices require 4,436clock cycles to initialize properly and enter user mode. Stratix III devicessupport a CLKUSR f MAX of 100 MHz.Altera Corporation 11–43May 2007 Stratix III Device Handbook, Volume 1