Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationFigure 7–7 shows the timing waveform for FPP configuration when usinga MAX II device as an external host. This waveform shows the timingwhen the decompression and/or the design security feature are enabled.Figure 7–7. FPP Configuration Timing Waveform With Decompression or Design Security FeatureEnabled Notes (1), (2)t CF2ST1t CFGnCONFIGt CF2CKt(3) nSTATUSSTATUS(4) CONF_DONEt CF2CDt CF2ST0t CHt CLDCLK1 2 3 4 1 2 3 4 (6) 14(5)DATA[7..0]t CLKByte 0 Byte 1 (6) Byte 2Byte n(5)User Modet ST2CKHigh-Zt DSUt DHt DHUser I/OUser ModeINIT_DONEt CD2UMNotes to Figure 7–7:(1) This timing waveform should be used when the decompression and/or design security feature are used.(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(3) Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.(4) Upon power-up, before and during configuration, CONF_DONE is low.(5) DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.(6) DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on thedual-purpose pin settings.(7) If needed, DCLK can be paused by holding it low. When DCLK restarts, the external host must provide data on theDATA[7..0] pins prior to sending the first DCLK rising edge.7–24 Altera CorporationStratix II Device Handbook, Volume 2 May 2007