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Configuration Handbook - Kamami.pl

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Fast Passive Parallel <strong>Configuration</strong>this option is turned off, the external system must monitor nSTATUS forerrors and then pulse nCONFIG low for at least 8 µs to restartconfiguration. The external system can pulse nCONFIG, if nCONFIG isunder system control rather than tied to V CC .In addition, if the configuration device sends all of its data and thendetects that CONF_DONE has not gone high, it recognizes that the FPGAhas not configured successfully. Enhanced configuration devices wait for64 DCLK cycles after the last configuration bit was sent for CONF_DONE toreach a high state. In this case, the configuration device pulls its OE pinlow, which in turn drives the target device’s nSTATUS pin low. If the Auto-Restart <strong>Configuration</strong> After Error option is set in the software, the targetdevice resets and then release its nSTATUS pin after a reset time-outperiod (maximum of 40 µs). When nSTATUS returns high, theconfiguration device will try to reconfigure the FPGA.When CONF_DONE is sensed low after configuration, the configurationdevice recognizes that the target device has not configured successfully;therefore, your system should not pull CONF_DONE low to delayinitialization. Instead, you should use the CLKUSR option to synchronizethe initialization of multi<strong>pl</strong>e devices that are not in the sameconfiguration chain. Devices in the same configuration chain willinitialize together if their CONF_DONE pins are tied together.If the optional CLKUSR pin is being used and nCONFIG is pulled low torestart configuration during device initialization, you need to ensureCLKUSR continues toggling during the time nSTATUS is low (maximumof 40 µs).When the FPGA is in user-mode, a reconfiguration can be initiated bypulling the nCONFIG pin low. The nCONFIG pin should be low for at least8 µs. When nCONFIG is pulled low, the FPGA also pulls nSTATUS andCONF_DONE low and all I/O pins are tri-stated. Since CONF_DONE ispulled low, this will activate the configuration device since it will see itsnCS pin drive low. Once nCONFIG returns to a logic high state andnSTATUS is released by the FPGA, reconfiguration begins.Figure 6–17 shows how to configure multi<strong>pl</strong>e APEX II devices with anenhanced configuration device. This circuit is similar to the configurationdevice circuit for a single device, except the APEX II devices are cascadedfor multi-device configuration.6–34 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 1 August 2005

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