Configuration Handbook - Kamami.pl

Device Configuration PinsJTAG pins must be kept stable before and during configuration. JTAG pinstability prevents accidental loading of JTAG instructions. Table 6–11describes the dedicated JTAG pins.Table 6–11. Dedicated JTAG PinsPin Name User Mode Pin Type DescriptionTDI N/A Input Serial input pin for instructions as well as test and programming data. Datais shifted in on the rising edge of TCK.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting this pin to V CC .TDO N/A Output Serial data output pin for instructions as well as test and programming data.Data is shifted out on the falling edge of TCK. The pin is tri-stated if data isnot being shifted out of the device.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by leaving this pin unconnected.TMS N/A Input Input pin that provides the control signal to determine the transitions of theTAP controller state machine. Transitions within the state machine occur onthe rising edge of TCK. Therefore, TMS must be set up before the risingedge of TCK. TMS is evaluated on the rising edge of TCK.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting this pin to V CC .TCK N/A Input The clock input to the BST circuitry. Some operations occur at the risingedge, while others occur at the falling edge.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting this pin to GND.TRST N/A Input Active-low input to asynchronously reset the boundary-scan circuit. TheTRST pin is optional according to IEEE Std. 1149.1.If the JTAG interface is not required on the board, the JTAG circuitry can bedisabled by connecting this pin to GND.6–68 Altera CorporationConfiguration Handbook, Volume 1 August 2005