Configuration Handbook - Kamami.pl

Configuration SchemesPS Configuration with Configuration DevicesThe configuration device scheme uses an Altera configuration device tosupply data to the Stratix or Stratix GX device in a serial bitstream (seeFigure 11–3).In the configuration device scheme, nCONFIG is usually tied to V CC(when using EPC16, EPC8, EPC4, or EPC2 devices, nCONFIG may beconnected to nINIT_CONF). Upon device power-up, the target Stratix orStratix GX device senses the low-to-high transition on nCONFIG andinitiates configuration. The target device then drives the open-drainCONF_DONE pin low, which in-turn drives the configuration device’s nCSpin low. When exiting power-on reset (POR), both the target andconfiguration device release the open-drain nSTATUS pin.Before configuration begins, the configuration device goes through a PORdelay of up to 200 ms to allow the power supply to stabilize (power theStratix or Stratix GX device before or during the POR time of theconfiguration device). This POR delay has a maximum of 200 ms forEPC2 devices. For enhanced configuration devices, you can selectbetween 2 ms and 100 ms by connecting PORSEL pin to VCC or GND,accordingly. During this time, the configuration device drives its OE pinlow. This low signal delays configuration because the OE pin is connectedto the target device’s nSTATUS pin. When the target and configurationdevices complete POR, they release nSTATUS, which is then pulled highby a pull-up resistor.When configuring multiple devices, configuration does not begin until alldevices release their OE or nSTATUS pins. When all devices are ready, theconfiguration device clocks data out serially to the target devices using aninternal oscillator.After successful configuration, the Stratix FPGA starts initialization usingthe 10-MHz internal oscillator as the reference clock. After initialization,this internal oscillator is turned off. The CONF_DONE pin is released by thetarget device and then pulled high by a pull-up resistor. Wheninitialization is complete, the FPGA enters user mode. The CONF_DONEpin must have an external 10-kΩ pull-up resistor in order for the deviceto initialize.If an error occurs during configuration, the target device drives itsnSTATUS pin low, resetting itself internally and resetting theconfiguration device. If the Auto-Restart Configuration on Frame Erroroption—available in the Quartus II Global Device Options dialog box(Assign menu)—is turned on, the device reconfigures automatically if anerror occurs. To find this option, choose Compiler Settings (Processingmenu), then click on the Chips & Devices tab.11–8 Altera CorporationStratix Device Handbook, Volume 2 July 2005