Configuration Handbook - Kamami.pl

Configuring Cyclone FPGAsTable 13–11 describes the optional configuration pins. If these optionalconfiguration pins are not enabled in the Quartus II software, they areavailable as general-purpose user I/O pins. Therefore duringconfiguration, these pins function as user I/O pins and are tri-stated withweak pull-ups.Table 13–11. Optional Cyclone Device Configuration PinsPin Name User Mode Pin Type DescriptionCLKUSRN/A if option ison, I/O if option isoffINIT_DONE N/A if option ison, I/O if option isoffDEV_OEDEV_CLRnN/A if the optionis on, I/O if theoption is off.N/A if the optionis on, I/O if theoption is off.InputOutputopen-drainInputInputOptional user-supplied clock input. Synchronizes theinitialization of one or more devices. This pin is enabled byturning on the Enable user-supplied start-up clock (CLKUSR)option in the Quartus II software.Status pin. Can be used to indicate when the device hasinitialized and is in user mode. The INIT_DONE pin must bepulled to V CC with a 10-kΩ resistor. The INIT_DONE pin driveslow during configuration. Before and after configuration, theINIT_DONE pin is released and is pulled to V CC by an externalpull-up resistor. Because INIT_DONE is tri-stated beforeconfiguration, it is pulled high by the external pull-up resistor.Thus, the monitoring circuitry must be able to detect a low-tohightransition. This pin is enabled by turning on the EnableINIT_DONE output option in the Quartus II software.Optional pin that allows the user to override all tri-states on thedevice. When this pin is driven low, all I/O pins are tri-stated;when this pin is driven high, all I/O pins behave as programmed.This pin is enabled by turning on the Enable device-wideoutput enable (DEV_OE) option in the Quartus II software.Optional pin that allows you to override all clears on all deviceregisters. When this pin is driven low, all registers are cleared;when this pin is driven high, all registers behave as programmed.This pin is enabled by turning on the Enable device-wide reset(DEV_CLRn) option in the Quartus II software.Table 13–12 describes the dedicated JTAG pins. JTAG pins must be keptstable before and during configuration to prevent accidental loading ofJTAG instructions.Altera Corporation 13–49January 2007 Cyclone Device Handbook, Volume 1