Configuration Handbook - Kamami.pl

Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data SheetThe DCLK frequency is limited by the maximum DCLK frequency theFPGA supports.fThe maximum DCLK input frequency supported by the FPGA isspecified in the appropriate FPGA family chapter in the ConfigurationHandbook.The controller chip features a programmable oscillator that can outputfour different frequencies. The various settings generate clock outputs atfrequencies as high as 10, 33, 50, and 66 MHz, as shown in Table 2–5.Table 2–5. Internal Oscillator FrequenciesFrequency Setting Min (MHz) Typ (MHz) Max (MHz)10 6.4 8.0 10.033 21.0 26.5 33.050 32.0 40.0 50.066 42.0 53.0 66.0Clock source, oscillator frequency, and clock divider (N) settings can bemade in the Quartus II software, by accessing the Configuration DeviceOptions inside the Device Settings window or the ConvertProgramming Files window. The same window can be used to selectbetween the internal oscillator and the external clock (EXCLK) input pinas your configuration clock source. The default setting selects the internaloscillator at the 10 MHz setting as the clock source, with a divide factorof 1.fFor more information on making the configuration clock source,frequency, and divider settings, refer to the Using Altera EnhancedConfiguration Devices chapter in the Configuration Handbook, Volume 2.Flash In-System Programming (ISP)The flash memory inside enhanced configuration devices can beprogrammed in-system via the JTAG interface and the external flashinterface. JTAG-based programming is facilitated by the configurationcontroller in the enhanced configuration device. External flash interfaceprogramming requires an external processor or FPGA to control the flash.1 The enhanced configuration device flash memory supports100,000 erase cycles.Altera Corporation 2–19May 2007 Configuration Handbook, Volume 2