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Configuration Handbook - Kamami.pl

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Enhanced <strong>Configuration</strong> Devices (EPC4, EPC8 & EPC16) Data SheetProtecting Intel Flash in EPC16 DevicesAltera recommends the following steps to protect the Intel flash in EPC16devices:1. Sequence the V CCW to less than 1 V during the flash V CC powertransitions.2. Isolate the V CCW from the V CC sup<strong>pl</strong>y on board.1 The lock bit protection is only supported using Sharp flash.Dynamic <strong>Configuration</strong> (Page Mode)The dynamic configuration (or page mode) feature allows the enhancedconfiguration device to store up to eight different sets of designs for allthe FPGAs in your system. You can then choose which page (set ofconfiguration files) the enhanced configuration device should use forFPGA configuration.Dynamic configuration or the page mode feature enables you to store aminimum of two pages: a factory default or fail-safe configuration, andan ap<strong>pl</strong>ication configuration. The fail-safe configuration page could beprogrammed during system production, while the ap<strong>pl</strong>icationconfiguration page could support remote or local updates. These remoteupdates could add or enhance system features and performance.However, with remote update capabilities comes the risk of possiblecorruption of configuration data. In the event of such a corruption, thesystem could automatically switch to the fail-safe configuration andavoid system downtime.The enhanced configuration device page mode feature works with theStratix Remote System <strong>Configuration</strong> feature, to enable intelligent remoteupdates to your systems.fFor more information on remotely updating Stratix FPGAs, refer toUsing Remote System <strong>Configuration</strong> with Stratix & Stratix GX Devices in theStratix Device <strong>Handbook</strong>.The three PGM[2..0] input pins control which page is used forconfiguration, and these pins are sam<strong>pl</strong>ed at the start of eachconfiguration cycle when OE goes high. The page mode selection allowsyou to dynamically reconfigure the functionality of your FPGA(s) byswitching the PGM[2..0] pins and asserting nCONFIG. Page 0 is definedas the default page and the PGM[2] pin is the most significant bit (MSB).Altera Corporation 2–15May 2007 <strong>Configuration</strong> <strong>Handbook</strong>, Volume 2

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