Configuration Handbook - Kamami.pl

Configuring Cyclone FPGAsTable 13–5. PS Timing Parameters for Cyclone Devices Note (1) (Part 2 of 2)Symbol Parameter Min Max Unitst CL DCLK low time 7 nst CLK DCLK period 15 nsf MAX DCLK maximum frequency 66 MHzt CD2UM CONF_DONE high to user mode (3) 6 20 µsNotes to Table 13–5:(1) This information is preliminary.(2) This value applies only if the internal oscillator is selected as the clock source for device initialization. If the clocksource is CLKUSR, multiply the clock period by 270 to obtain this value. CLKUSR must be running during thisperiod to reset the device.(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for deviceinitialization. If the clock source is CLKUSR, multiply the clock period by 140 to obtain this value.(4) You can obtain this value if you do not delay configuration by extending the nSTATUS low-pulse width.fDevice configuration options and how to create configuration files arediscussed further in the Software Settings chapter in Volume II of theConfiguration Handbook.JTAG-Based ConfigurationJTAG has developed a specification for boundary-scan testing. Thisboundary-scan test (BST) architecture offers the capability to efficientlytest components on printed circuit boards (PCBs) with tight lead spacing.The BST architecture can test pin connections without using physical testprobes and capture functional data while a device is operating normally.You can also use the JTAG circuitry to shift configuration data intoCyclone FPGAs. The Quartus II software automatically generates .soffiles that can be used for JTAG configuration.fFor more information on JTAG boundary-scan testing, seeAN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.To use the SignalTap II Embedded Logic Analyzer, you need to connectthe JTAG pins of your Cyclone device to a download cableheader on yourPCB.fFor more information on SignalTap II, see the Design Debugging Using theSignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook.Cyclone devices are designed such that JTAG instructions haveprecedence over any device operating modes. So JTAG configuration cantake place without waiting for other configuration to complete (e.g.,configuration with serial or enhanced configuration devices). If youAltera Corporation 13–31January 2007 Cyclone Device Handbook, Volume 1