Configuration Handbook - Kamami.pl

Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data SheetPowerSequencingAltera requires that you power-up the FPGA's V CCINT supply before theenhanced configuration device's POR expires.Power up needs to be controlled so that the enhanced configurationdevice’s OE signal goes high after the CONF_DONE signal is pulled low. Ifthe EEPC device exits POR before the FPGA is powered up, theCONF_DONE signal will be high since the pull-up resistor is holding thissignal high. When the enhanced configuration device exits POR, OE isreleased and pulled high by a pull-up resistor. Since the enhancedconfiguration device samples the nCS signal on the rising edge of OE, itdetects a high level on CONF_DONE and enters an idle mode. DATA andDCLK outputs will not toggle in this state and configuration will notbegin. The enhanced configuration device will only exit this mode if it ispowered down and then powered up correctly.1 To ensure the enhanced configuration device entersconfiguration mode properly, you need to ensure that the FPGAcompletes power-up before the enhanced configuration deviceexits POR.The pin-selectable POR time feature is useful for ensuring this power-upsequence. The enhanced configuration device has two POR settings, 2 mswhen PORSEL is set to a high level and 100 ms when PORSEL is set to alow level. For more margin, the 100-ms setting can be selected to allow theFPGA to power-up before configuration is attempted.Alternatively, a power-monitoring circuit or a power-good signal can beused to keep the FPGA’s nCONFIG pin asserted low until both supplieshave stabilized. This ensures the correct power up sequence forsuccessful configuration.Programming &ConfigurationFile SupportfThe Quartus II development software provides programming support forthe enhanced configuration device and automatically generates the POFfiles for the EPC4, EPC8, and EPC16 devices. In a multi-device project, thesoftware can combine the SOF files for multiple Stratix series, Cycloneseries, APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K FPGAsinto one programming file for the enhanced configuration device.Refer to the Using Altera Enhanced Configuration Devices chapter in theConfiguration Handbook, Volume 2, or refer to the Software Settings sectionin the Configuration Handbook for details on generating programmingfiles.Altera Corporation 2–27May 2007 Configuration Handbook, Volume 2