Configuration Handbook - Kamami.pl

Configuring Cyclone FPGAsFigure 13–17. PS Configuration Circuit with a MicroprocessorMemoryADDRDATA0V CCV CCV CC (2)10 kΩ 10 kΩCyclone DeviceCONF_DONEnSTATUSMSEL0MSEL1MicroprocessorGNDnCEGNDnCEO N.C. (1)DATA0nCONFIGDCLKNotes to Figure 13–17:(1) The nCEO pin is left unconnected.(2) Connect MSEL0 to the V CC supply voltage of the I/O bank it resides in.Configuring Cyclone FPGAs with the MicroBlaster SoftwareThe MicroBlaster TM software driver allows you to configure AlteraFPGAs, including Cyclone FPGAs, through the ByteBlaster II orByteBlasterMV cable in PS mode. The MicroBlaster software driversupports a Raw Binary File (.rbf) programming input file and is targetedfor embedded PS configuration. The source code is developed for theWindows NT operating system, although you can customize it to run onother operating systems. For more information on the MicroBlastersoftware driver, see the Configuring the MicroBlaster Passive Serial SoftwareDriver White Paper and source files on the Altera web site atwww.altera.com.Passive Serial TimingFor successful configuration using the PS scheme, several timingparameters such as setup, hold, and maximum clock frequency must besatisfied. The enhanced configuration and EPC2 devices are designed tomeet these interface timing specifications. If you use a microprocessor oranother intelligent host to control the PS interface, ensure that you meetthese timing requirements.Altera Corporation 13–29January 2007 Cyclone Device Handbook, Volume 1