Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationFigure 11–7 shows the timing waveform for FPP configuration whenusing a MAX II device as an external host. This waveform shows thetiming when the decompression and/or the design security feature areenabled.Figure 11–7. FPP Configuration Timing Waveform With Decompression or Design Security Feature EnabledNotes (1), (2)nCONFIGt CFGt CF2ST1t CF2CKt(3) nSTATUSSTATUS(4) CONF_DONEt CF2CDt CF2ST0t CHt CLDCLK1 2 3 4 1 2 3 4 (6) 14(5)DATA[7..0]t CLKByte 0 Byte 1 (6) Byte 2Byte n(5)User ModeUser I/Ot ST2CKHigh-Zt DSUt DHt DHUser ModeINIT_DONEt CD2UMNotes to Figure 11–7:(1) You should use this timing waveform when the decompression and/or design security features are used.(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(3) Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.(4) Upon power-up, before and during configuration, CONF_DONE is low.(5) You should not leave DCLK floating after configuration. You should drive it high or low, whichever is moreconvenient.(6) DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purposepin settings.(7) If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on theDATA[7..0] pins prior to sending the first DCLK rising edge.11–20 Altera CorporationStratix III Device Handbook, Volume 1 May 2007