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Configuration Handbook - Kamami.pl

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JTAG <strong>Configuration</strong>During JTAG configuration, data can be downloaded to the device on thePCB through the USB Blaster, MasterBlaster, ByteBlaster II, orByteBlasterMV header. Configuring devices through a cable is similar toprogramming devices in-system, except the TRST pin should beconnected to V CC . This ensures that the TAP controller is not reset.Figure 6–29. shows JTAG configuration of a single APEX II device.Figure 6–29. JTAG <strong>Configuration</strong> of a Single Device Using a Download CableVCC (1)(1) VCC(1) VCC 1 kΩ1 kΩGND N.C.APEX II DevicenCE (4)TCKnCE0TDO1 kΩVCC (1)1 kΩ(2)(2)(2)nSTATUSCONF_DONEnCONFIGMSEL0MSEL1TMSTDITRSTVCCDownload Cable10-Pin Male Header(JTAG Mode)(Top View)Pin 1VCCGNDVIO (3)1 kΩGNDGNDNotes to Figure 6–29:(1) The pull-up resistor should be connected to the same sup<strong>pl</strong>y voltage as the USB Blaster, MasterBlaster (VIO pin),ByteBlaster II, or ByteBlasterMV cable.(2) The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If onlyJTAG configuration is used, connect nCONFIG to V CC , and MSEL0 and MSEL1 to ground.(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’sV CCIO . Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In theByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when itis used for Active Serial programming, otherwise it is a no connect.(4) nCE must be connected to GND or driven low for successful JTAG configuration.To configure a single device in a JTAG chain, the programming software<strong>pl</strong>aces all other devices in BYPASS mode. In BYPASS mode, devices passprogramming data from the TDI pin to the TDO pin through a singlebypass register without being affected internally. This scheme enables theprogramming software to program or verify the target device.<strong>Configuration</strong> data driven into the device appears on the TDO pin oneclock cycle later.6–58 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 1 August 2005

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