Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesYou also have the flexibility to synchronize initialization of multipledevices or to delay initialization with the CLKUSR option. The Enableuser-supplied start-up clock (CLKUSR) option can be turned on in theQuartus II software from the General tab of the Device & Pin Optionsdialog box. Supplying a clock on CLKUSR will not affect the configurationprocess. After all configuration data has been accepted and CONF_DONEgoes high, CLKUSR will be enabled after the time specified as t CD2CU . Afterthis time period elapses, Stratix II and Stratix II GX devices require 299clock cycles to initialize properly and enter user mode. Stratix II andStratix II GX devices support a CLKUSR f MAX of 100 MHz.An optional INIT_DONE pin is available, which signals the end ofinitialization and the start of user-mode with a low-to-high transition.The Enable INIT_DONE Output option is available in the Quartus IIsoftware from the General tab of the Device & Pin Options dialog box.If the INIT_DONE pin is used it will be high due to an external 10-kΩpull-up resistor when nCONFIG is low and during the beginning ofconfiguration. Once the option bit to enable INIT_DONE is programmedinto the device (during the first frame of configuration data), theINIT_DONE pin will go low. When initialization is complete, theINIT_DONE pin will be released and pulled high. The MAX II devicemust be able to detect this low-to-high transition which signals the devicehas entered user mode. When initialization is complete, the device entersuser mode. In user-mode, the user I/O pins will no longer have weakpull-up resistors and will function as assigned in your design.To ensure DCLK and DATA0 are not left floating at the end ofconfiguration, the MAX II device must drive them either high or low,whichever is convenient on your board. The DATA[0] pin is available asa user I/O pin after configuration. When the PS scheme is chosen in theQuartus II software, as a default this I/O pin is tri-stated in user modeand should be driven by the MAX II device. To change this default optionin the Quartus II software, select the Dual-Purpose Pins tab of the Device& Pin Options dialog box.The configuration clock (DCLK) speed must be below the specifiedfrequency to ensure correct configuration. No maximum DCLK periodexists, which means you can pause configuration by halting DCLK for anindefinite amount of time.If an error occurs during configuration, the device drives its nSTATUS pinlow, resetting itself internally. The low signal on the nSTATUS pin alsoalerts the MAX II device that there is an error. If the Auto-restartconfiguration after error option (available in the Quartus II softwarefrom the General tab of the Device & Pin Options dialog box) is turnedon, the Stratix II or Stratix II GX device releases nSTATUS after a resettime-out period (maximum of 100 µs). After nSTATUS is released andAltera Corporation 7–49May 2007 Stratix II Device Handbook, Volume 2