ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.3 Register descriptionsThis section describes all the CP15 system control registers by coprocessor register numberorder. Table 4-2 on page 4-4 to Table 4-15 on page 4-13 provide cross references to individualregisters.4.3.1 Main ID RegisterThe MIDR characteristics are:PurposeProvides identification information for the processor, including animplementer code for the device and a part number.Usage constraints The MIDR is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-1 shows the MIDR bit assignments.31 24 23 20 19 16 15 4 3 0ImplementerVariantArchitecture Primary part number RevisionFigure 4-1 MIDR bit assignmentsTable 4-29 shows the MIDR bit assignments.Table 4-29 MIDR bit assignmentsBits Name Function[31:24] Implementer Indicates the implementer code:0x41 ARM Limited.[23:20] Variant Indicates the variant number of the processor. This is the major revision number n in the rn partof the rnpn description of the product revision status:0x4Major revision number.[19:16] Architecture Indicates the architecture code:0xF Defined by CPUID scheme.[15:4] Primary part number Indicates the primary part number:0xC0F Cortex-A15.[3:0] Revision Indicates the minor revision number of the processor. This is the minor revision number n in thepn part of the rnpn description of the product revision status:0x0Minor revision number.To access the MIDR, read the CP15 register with:MRC p15, 0, , c0, c0, 0; Read Main ID RegisterARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-27ID062913Non-Confidential