ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control• Is only accessible from PL1 or higher, with access rights that dependon the mode:— Read/write in Secure PL1 modes.— Read-only and write-ignored in Non-secure PL1 and PL2modes.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-14 on page 4-13.Figure 4-60 shows the L2PFR bit assignments.31 13 12 11 10 9 8 7 6 5 4 3 0ReservedReservedDisable dynamic throttling of load/store prefetch requestsEnable prefetch requests from ReadUnique transactionsDisable table walk descriptor access prefetchReservedL2 instruction fetch prefetch distanceReservedL2 load/store data prefetch distanceTable 4-75 shows the L2PFR bit assignments.Figure 4-60 L2PFR bit assignmentsTable 4-75 L2 Prefetch Control Register bit assignmentsBits Name Function[31:13] - Reserved, RAZ/WI.[12] Disable dynamic throttling of load/storeprefetch requests[11] Enable prefetch requests from ReadUniquetransactions[10] Disable table walk descriptor accessprefetchDisable dynamic throttling of load/store prefetch requests:0 Enables dynamic throttling of load/store prefetch requestsThis is the reset value.1 Disables dynamic throttling of load/store prefetch requests.Enable prefetch requests from ReadUnique transactions:0 Disables prefetch requests from being generated byReadUnique transactions.1 Enables prefetch requests to be generated by ReadUniquetransactions. This is the reset value.Disables table walk descriptor access prefetch:0 Enables table walk descriptor access prefetch. This is thereset value.1 Disables table walk descriptor access prefetch.[9] - Reserved, RAZ/WI.[8:7] L2 instruction fetch prefetch distance Indicates the L2 instruction fetch prefetch distance:b000 cache line, disables instruction prefetch.b011 cache line.b102 cache lines.b113 cache lines. This is the reset value.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-104ID062913Non-Confidential