ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-10 c9 register summary (continued)Op1 CRm Op2 Name Reset Description1 PMXEVTYPER UNK Performance Monitor Event Type Select Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition2 PMXEVCNTR UNK Performance Monitor Event Count Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionc14 0 PMUSERENR 0x00000000 Performance Monitor User Enable Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition1 PMINTENSET UNK Performance Monitor Interrupt Enable Set Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition2 PMINTENCLR UNK Performance Monitor Interrupt Enable Clear Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition3 PMOVSSET UNK Performance Monitor Overflow Flag Status Set Register, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-Redition1 c0 2 L2CTLR 0x00000000 a L2 Control Register on page 4-853 L2ECTLR 0x00000000 L2 Extended Control Register on page 4-87a. The reset value depends on the processor configuration.4.2.10 c10 registersTable 4-11 shows the 32-bit wide CP15 system control registers when CRn is c10.Table 4-11 c10 register summaryOp1 CRm Op2 Name Reset Description0 c2 0 PRRR a 0x00098AA4 Primary Region Remap Register, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition0 MAIR0 b 0x00098AA4 Memory Attribute Indirection Register 0 on page 4-881 NMRR c 0x44E048E0 Normal Memory Remap Register, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition1 MAIR1 d 0x44E048E0 Memory Attribute Indirection Register 1 on page 4-89c3 0 AMAIR0 UNK Auxiliary Memory Attribute Indirection Register 0 on page 4-891 AMAIR1 UNK Auxiliary Memory Attribute Indirection Register 1 on page 4-894 c2 0 HMAIR0 UNK Hyp Memory Attribute Indirection Register 0, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition1 HMAIR1 UNK Hyp Memory Attribute Indirection Register 1, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionc3 0 HAMAIR0 UNK Hyp Auxiliary Memory Attribute Indirection Register 0 on page 4-891 HAMAIR1 UNK Hyp Auxiliary Memory Attribute Indirection Register 1 on page 4-89a. The processor behavior for all implementation-defined encodings in the PRRR register is UNPREDICTABLE.b. The processor behavior for all implementation-defined encodings in the MAIR0 register is UNPREDICTABLE.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-11ID062913Non-Confidential