ARM Cortex-A15 MPCore Processor Technical Reference Manual

Performance Monitor Unit11.4 PMU register descriptionsThis section describes the Cortex-A15 MPCore PMU registers. Table 11-1 on page 11-4provides cross references to individual registers.11.4.1 Performance Monitor Configuration RegisterThe PMCFGR characteristics are:PurposeContains PMU-specific configuration data.This register is visible only in the memory-mapped views of thePerformance Monitors registers.Usage constraints There are no usage constraints.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 11-1 on page 11-4.Figure 11-2 shows the PMCFGR bit assignments.31 20 19 18 17 16 15 14 13 8 7 0Reserved 1 (0) (0) 1 1 0 1 1 1 1 1NSIZECCCCDEXUENFigure 11-2 PMCFGR bit assignmentsTable 11-2 shows the PMCFGR bit assignments.Table 11-2 PMCFGR bit assignmentsBits Name Function[31:20] - Reserved.[19] UEN User mode enable register supported bit. This bit is RAO:1 User mode enable register implemented.[18:17] - Reserved.[16] EX Export supported:1 Export is supported. PMCR.X is writable.[15] CCD Cycle counter clock divider implemented. This bit is RAO:1 The cycle count divider implemented. PMCR.D is writable.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-7ID062913Non-Confidential