ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 10 7 6 3 2 1 00TE 1 1 0 0 EE 0 1 1 0 0 1 0 1 0 0 0 I 1 0 0 0 0 1 1 1 1 C AMWXNFigure 4-28 HSCTLR bit assignmentsTable 4-57 shows the HSCTLR bit assignments.Table 4-57 HSCTLR bit assignmentsBits Name Function[31] - Reserved, RAZ/WI.[30] TE Thumb Exception enable. This bit controls whether exceptions taken in Hyp mode are taken inARM or Thumb state:0 Exceptions taken in ARM state.1 Exceptions taken in Thumb state.[29:28] - Reserved, RAO/WI.[27:26] - Reserved, RAZ/WI.[25] EE Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry to anexception vector in Hyp mode. This value also indicates the endianness of the translation tabledata for translation table lookups, when executing in Hyp mode:0 Little endian.1 Big endian.[24] - Reserved, RAZ/WI.[23:22] - Reserved, RAO/WI.[21] FI Fast Interrupts configuration enable bit. This bit can be used to reduce interrupt latency bydisabling IMPLEMENTATION DEFINED performance features.This bit is not implemented, RAZ/WI.[20] - Reserved, RAZ/WI.[19] WXN Write permission implies Execute Never (XN):0 Hyp translations that permit write are not forced to XN.1 Hyp translations that permit write are forced to XN.[18] - Reserved, RAO/WI.[17] - Reserved, RAZ/WI.[16] - Reserved, RAO/WI.[15:13] - Reserved, RAZ/WI.[12] I Instruction cache enable bit. This is a global enable bit for instruction caches, for memory accessesmade in Hyp mode:0 Instruction caches disabled.1 Instruction caches enabled.[11] - Reserved, RAO/WI.[10:7] - Reserved, RAZ/WI.[6:3] - Reserved, RAO/WI.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-68ID062913Non-Confidential